公开(公告)号：US11082092B2

公开(公告)日：2021-08-03

申请号：US16260945

申请日：2019-01-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Sylvie Wuidart ,  Sophie Maurice

IPC: H04B5/00 ,  G06F21/60 ,  H04W88/18 ,  H04W4/80 ,  H04W88/02 ,  G06K7/10

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

公开(公告)号：US09012911B2

公开(公告)日：2015-04-21

申请号：US14085565

申请日：2013-11-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Alexandre Sarafianos

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/576 ,  G06F21/75 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L2924/0002 ,  Y10T307/76 ,  H01L2924/00

Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.

Abstract translation: 一种集成电路，包括：第一导电类型的半导体衬底; 所述第一导电类型的多个区域从所述基板的表面垂直延伸，每个所述区域沿着其外围沿着所述第二导电类型的区域横向界定; 以及用于检测第一导电类型的每个区域和用于将衬底偏压的区域之间的衬底电阻变化为参考电压的装置。

公开(公告)号：US12267126B2

公开(公告)日：2025-04-01

申请号：US18125024

申请日：2023-03-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvie Wuidart ,  Sophie Maurice

IPC: H04B5/00 ,  G06F21/60 ,  G06K7/10 ,  G08C15/06 ,  H04B5/72 ,  H04W88/18 ,  H04W4/80 ,  H04W88/02

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

公开(公告)号：US11637590B2

公开(公告)日：2023-04-25

申请号：US17364291

申请日：2021-06-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvie Wuidart ,  Sophie Maurice

IPC: G05B11/01 ,  H04B5/00 ,  G06F21/60 ,  H04W88/18 ,  H04W4/80 ,  H04W88/02 ,  G06K7/10

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

公开(公告)号：US20150340426A1

公开(公告)日：2015-11-26

申请号：US14715814

申请日：2015-05-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Sylvie Wuidart ,  Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/423 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42356 ,  H01L29/66181 ,  H01L29/7842 ,  H01L29/94 ,  H01L29/945

Abstract: An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region.

Abstract translation: 集成电路包括基板和至少部分地设置在由绝缘区域限制的基板的有源区域内的电路部件（诸如MOS器件或电阻）。 结合绝缘区域提供包括第一电极（用于连接到第一电位例如接地）和第二电极（用于连接到第二电位例如电源电压）的电容结构。 第一和第二电极之一至少部分地位于绝缘区域内。 因此，电容结构被配置为允许有效区域内的压缩应力的降低。

公开(公告)号：US09224701B2

公开(公告)日：2015-12-29

申请号：US14667232

申请日：2015-03-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Sylvie Wuidart ,  Alexandre Sarafianos

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/66 ,  G06F21/75

CPC classification number: H01L23/576 ,  G06F21/75 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L2924/0002 ,  Y10T307/76 ,  H01L2924/00

Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.