公开(公告)号：US20190088735A1

公开(公告)日：2019-03-21

申请号：US16197011

申请日：2018-11-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frédéric Lanois ,  Alexei Ankoudinov ,  Vladimir Rodov

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/861 ,  H01L27/06 ,  H02M3/158 ,  H01L27/092

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

公开(公告)号：US20170301752A1

公开(公告)日：2017-10-19

申请号：US15365335

申请日：2016-11-30

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frédéric Lanois ,  Alexei Ankoudinov ,  Vladimir Rodov

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H02M3/158 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/7802 ,  H01L29/861 ,  H02M3/158

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

公开(公告)号：US10903311B2

公开(公告)日：2021-01-26

申请号：US16197011

申请日：2018-11-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frédéric Lanois ,  Alexei Ankoudinov ,  Vladimir Rodov

IPC: H01L27/06 ,  H01L29/86 ,  H01L29/06 ,  H01L29/861 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H02M3/158 ,  H01L27/092

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.

公开(公告)号：US10177218B2

公开(公告)日：2019-01-08

申请号：US15365335

申请日：2016-11-30

Applicant: STMicroelectronics (Tours) SAS

Inventor： Frédéric Lanois ,  Alexei Ankoudinov ,  Vladimir Rodov

IPC: H02M3/158 ,  H01L29/06 ,  H01L29/861 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L27/06 ,  H01L27/092

Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.