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    Reduction of noise in touch data samples via sampling during porch time of Vsync and Hsync signals
    1.
    发明授权
    Reduction of noise in touch data samples via sampling during porch time of Vsync and Hsync signals 有权

    公开(公告)号：US10558311B2

    公开(公告)日：2020-02-11

    申请号：US16117277

    申请日：2018-08-30

    申请人： STMicroelectronics Asia Pacific Pte Ltd

    发明人： Baranidharan Karuppusamy ,  Chaochao Zhang ,  Kusuma Adi Ningrat

    IPC分类号： G06F3/044 ,  G06F3/041

    摘要： Disclosed herein is a touch screen controller for controlling touch sensing in a touch screen display, the touch screen display having a display layer controlled as a function of horizontal sync and vertical sync signals and a capacitive touch array comprised of drive lines and sense lines. The touch screen controller includes a driver and control circuitry. The control circuitry is configured to cause the driver to generate a driving signal on the drive lines during assertion of the horizontal sync signal, and cause the driver to generate the driving signal on the drive lines during assertion of the vertical sync signal. Analog touch sensing circuitry is configured to generate analog touch data as a function of signals on the sense lines resulting from generation of the drive signal on the drive lines.

    METHOD AND APPARATUS FOR BLOCKING ACCUMULATION OF ELECTRICAL FAST TRANSIENT (EFT) NOISE
    2.
    发明申请
    METHOD AND APPARATUS FOR BLOCKING ACCUMULATION OF ELECTRICAL FAST TRANSIENT (EFT) NOISE 有权
    阻塞电气瞬态（EFT）噪声累积的方法和装置

    公开(公告)号：US20160378222A1

    公开(公告)日：2016-12-29

    申请号：US14753129

    申请日：2015-06-29

    申请人： STMicroelectronics Asia Pacific Pte Ltd

    发明人： Chee Weng Cheong ,  EngJye Ng ,  Dianbo Guo ,  Chaochao Zhang ,  Kusuma Adi Ningrat

    IPC分类号： G06F3/044

    CPC分类号： G06F3/044

    摘要： A charge sensing circuit generates a voltage in a sensing period that is indicative of sensed charge. The generated voltages are accumulated by an accumulator circuit over a number of sensing periods. A noise detection circuit senses when the voltage generated by the charge sensing circuit is outside of a boundary and generates a detection signal in response thereto. A control circuit, in response to the detection signal, controls the accumulator circuit to block accumulation of the voltages generated by the charge sensing circuit during at least the sensing period in which the detection signal is generated. An analog-to-digital converter circuit then converts an accumulated output voltage from the accumulator circuit to a digital value at the end of an accumulation time period that includes the sensing periods. The end of the accumulation time period is delayed by at least one sensing period in response to the detection signal.

    摘要翻译： 电荷感测电路在感测周期中产生指示感测电荷的电压。 所产生的电压在多个感测周期上由累加器电路累积。 噪声检测电路检测由电荷感测电路产生的电压何时在边界之外，并响应于此产生检测信号。 响应于检测信号，控制电路在至少产生检测信号的感测周期期间控制累加器电路阻止由电荷感测电路产生的电压的累积。 然后，模数转换器电路在包括感测周期的累积时间周期结束时将来自累加器电路的累积输出电压转换为数字值。 积累时间段的结束响应于检测信号延迟至少一个感测周期。

    Method and apparatus for blocking accumulation of electrical fast transient (EFT) noise
    3.
    发明授权
    Method and apparatus for blocking accumulation of electrical fast transient (EFT) noise 有权

    公开(公告)号：US09990091B2

    公开(公告)日：2018-06-05

    申请号：US14753129

    申请日：2015-06-29

    申请人： STMicroelectronics Asia Pacific Pte Ltd

    发明人： Chee Weng Cheong ,  EngJye Ng ,  Dianbo Guo ,  Chaochao Zhang ,  Kusuma Adi Ningrat

    IPC分类号： G06F3/045 ,  G06F3/044

    CPC分类号： G06F3/044

    摘要： A charge sensing circuit generates a voltage in a sensing period that is indicative of sensed charge. The generated voltages are accumulated by an accumulator circuit over a number of sensing periods. A noise detection circuit senses when the voltage generated by the charge sensing circuit is outside of a boundary and generates a detection signal in response thereto. A control circuit, in response to the detection signal, controls the accumulator circuit to block accumulation of the voltages generated by the charge sensing circuit during at least the sensing period in which the detection signal is generated. An analog-to-digital converter circuit then converts an accumulated output voltage from the accumulator circuit to a digital value at the end of an accumulation time period that includes the sensing periods. The end of the accumulation time period is delayed by at least one sensing period in response to the detection signal.

    SYSTEM AND METHOD OF COMMUNICATION BETWEEN A CAPACITIVE TOUCH SCREEN AND AN ACTIVE STYLUS
    5.
    发明申请
    SYSTEM AND METHOD OF COMMUNICATION BETWEEN A CAPACITIVE TOUCH SCREEN AND AN ACTIVE STYLUS 有权
    电容触摸屏和活动板之间的通信系统和方法

    公开(公告)号：US20160048234A1

    公开(公告)日：2016-02-18

    申请号：US14461977

    申请日：2014-08-18

    申请人： STMicroelectronics Asia Pacific Pte Ltd

    发明人： Praveesh Chandran ,  Baranidharan Karuppusamy ,  Giuseppe Noviello ,  Chee Weng Cheong ,  Leonard Dinu ,  Dianbo Guo ,  Kien Beng Tan ,  Chaochao Zhang

    IPC分类号： G06F3/044 ,  G06F3/0354

    CPC分类号： G06F3/044 ,  G06F3/03545 ,  G06F3/0383 ,  G06F3/0416

    摘要： An active stylus is capacitively coupled to a capacitive touch panel for communication. The active stylus operates in a wait mode to receive initial communications from the panel. In response to such receipt, the active stylus synchronizes to a repeating communications frame implementing time division multiplexing. Communications from the active stylus to the panel include: information communications; synchronization communications and communications specific for columns and/or rows of the panel. Communications from the panel to the active stylus may be addressed uniquely to the stylus or commonly to a group of styluses.

    摘要翻译： 有源触笔电容耦合到用于通信的电容式触摸面板。 活动的笔在等待模式下操作以从面板接收初始通信。 响应于这样的接收，活动触针与实现时分复用的重复通信帧同步。 从活动手写笔到面板的通信包括：信息通信; 专用于面板的列和/或行的同步通信和通信。 从面板到活动手写笔的通信可以唯一地被寻址到手写笔，或者通常被发送到一组触控笔。

    Chip synchronization by a master-slave circuit
    7.
    发明授权
    Chip synchronization by a master-slave circuit 有权

    公开(公告)号：US09846665B2

    公开(公告)日：2017-12-19

    申请号：US14534091

    申请日：2014-11-05

    申请人： STMicroelectronics Asia Pacific Pte Ltd

    发明人： Chaochao Zhang ,  Chee Weng Cheong ,  Dianbo Guo

    IPC分类号： G06F13/364 ,  G06F5/06 ,  G06F13/42

    CPC分类号： G06F13/364 ,  G06F5/065 ,  G06F13/4282 ,  G06F2205/067

    摘要： A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.

    IIC bus start-stop detection circuit
    8.
    发明授权
    IIC bus start-stop detection circuit 有权
    IIC总线启停检测电路

    公开(公告)号：US09436647B2

    公开(公告)日：2016-09-06

    申请号：US14026375

    申请日：2013-09-13

    申请人： STMicroelectronics Asia Pacific Pte. Ltd.

    发明人： Nee Loong Wilson Low ,  Chaochao Zhang

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4282 ,  G06F13/42 ,  G06F13/4291 ,  G06F2213/0016

    摘要： A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.

    摘要翻译： 耦合起始/停止条件检测电路以从IIC总线接收SDA和SCL信号。 该电路响应于SDA信号的边缘产生第一信号，并响应于SCL信号的相反边沿而产生作为第二信号的第一信号的反相。 逻辑上组合第一和第二信号以产生输出信号。 电路响应的SDA和SCL信号的边缘的特定方向决定输出信号是指示启动条件检测还是停止条件检测。

    IIC BUS START-STOP DETECTION CIRCUIT
    9.
    发明申请
    IIC BUS START-STOP DETECTION CIRCUIT 有权
    IIC总线启动停止检测电路

    公开(公告)号：US20150081936A1

    公开(公告)日：2015-03-19

    申请号：US14026375

    申请日：2013-09-13

    申请人： STMicroelectronics Asia Pacific Pte. Ltd.

    发明人： Nee Loong Wilson Low ,  Chaochao Zhang

    IPC分类号： G06F13/38

    CPC分类号： G06F13/4282 ,  G06F13/42 ,  G06F13/4291 ,  G06F2213/0016

    摘要： A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.

    摘要翻译： 耦合起始/停止条件检测电路以从IIC总线接收SDA和SCL信号。 该电路响应于SDA信号的边缘产生第一信号，并响应于SCL信号的相反边沿而产生作为第二信号的第一信号的反相。 逻辑上组合第一和第二信号以产生输出信号。 电路响应的SDA和SCL信号的边缘的特定方向决定输出信号是指示启动条件检测还是停止条件检测。