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公开(公告)号：US10168363B1
公开(公告)日：2019-01-01
申请号：US15920896
申请日：2018-03-14
Inventor： Sandor Petenyi
Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.
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公开(公告)号：US20170194855A1
公开(公告)日：2017-07-06
申请号：US14986425
申请日：2015-12-31
Inventor： Sandor Petenyi
CPC classification number: G05F1/625
Abstract: A voltage regulator is controlled to improve supply voltage rejection by cancelling an alternating component of a supply voltage signal that is capacitively coupled to a high-impedance node within the voltage regulator. This cancellation is done by capacitively coupling an inverted version of the alternating component to the high-impedance node to thereby substantially cancel the alternating component present on the high-impedance node. The high-impedance node may be a high-impedance voltage reference node of the voltage regulator.
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公开(公告)号：US09645594B2
公开(公告)日：2017-05-09
申请号：US14881498
申请日：2015-10-13
Inventor： Sandor Petenyi
CPC classification number: G05F1/575
Abstract: A voltage regulator includes an input terminal to receive an input voltage, an output terminal to supply an output voltage, a power transistor, a differential amplifier, a driver, a dropout detector and a bias current limiter. The differential amplifier provides a drive signal based on a difference between a voltage reference and a feedback signal corresponding to the output voltage. The driver includes an impedance device, and a driver transistor that receives the drive signal so as to vary a bias current to a control terminal of the power transistor. The dropout detector and the bias current limiter is coupled to the input terminal, the impedance device, and the output terminal and includes first and second transistors coupled together, and a bias current generator coupled to the second transistor.
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公开(公告)号：US11652457B2
公开(公告)日：2023-05-16
申请号：US17362276
申请日：2021-06-29
Inventor： Sandor Petenyi
CPC classification number: H03F3/45179 , H03F1/0205 , H03F1/301 , H03F2200/78 , H03F2203/45
Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.
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公开(公告)号：US10788848B2
公开(公告)日：2020-09-29
申请号：US16285330
申请日：2019-02-26
Inventor： Sandor Petenyi
Abstract: An amplifier stage of an LDO regulator circuit includes an amplifier stage that generates a drive signal in response to a first voltage difference an output voltage of the LDO regulator circuit and a reference voltage. A drive stage having a quiescent current consumption is configured to generate a control signal in response to the drive signal. The control signal is applied to the control terminal of a power transistor. A dropout detector senses whether the LDO regulator circuit is operating in closed loop regulation mode or in open loop dropout mode by sensing a second difference in voltage between the drive signal and the control signal. A quiescent current limiter circuit responds to the sensed second difference by controlling the quiescent current consumption of the drive stage, and in particular limiting current consumption when the LDO regulator circuit is operating in the open loop dropout mode.
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Patent Agency Ranking
6.发明授权Method of preventing inversion of output current flow in a voltage regulator and related voltage regulator 有权防止电压调节器和相关电压调节器中输出电流反转的方法公开(公告)号：US09582017B2
公开(公告)日：2017-02-28
申请号：US14320999
申请日：2014-07-01
Inventor： Sandor Petenyi
CPC classification number: G05F1/625 , G05F1/569 , H02H7/1213 , H02J7/0072
Abstract: The reversal of the flow of output current in a voltage regulator is prevented by equipping the voltage regulator of a regulation transistor controlled by an analog voltage control, having its current terminals connected between the control terminal of the fifth transistor power of the regulator and the power supply line or the common ground node of the regulator. The regulation transistor is configured to provide an electrical path of conduction between the control terminal and the power supply line or the ground node and is controlled by an analog voltage control that varies in a continuous manner between a first level, suitable to extinguish the regulation transistor, and a second level suitable for biasing it in an operating condition of deep conduction, as the difference between the supply voltage and the regulated output voltage approaching an offset voltage.
Abstract translation: 通过装配由模拟电压控制器控制的调节晶体管的电压调节器来防止电压调节器中的输出电流的反转，其电流端子连接在调节器的第五晶体管功率的控制端和电源 供电线路或调节器的公共接地节点。 调节晶体管被配置为提供控制端与电源线或接地节点之间的导通电路，并且通过模拟电压控制来控制，该模拟电压控制以连续的方式在适于熄灭调节晶体管的第一电平之间变化 以及适于在深导通的操作条件下偏置它的第二电平，因为电源电压和调节的输出电压之间的差接近偏移电压。
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公开(公告)号：US11374579B2
公开(公告)日：2022-06-28
申请号：US17227974
申请日：2021-04-12
Inventor： Sandor Petenyi
Abstract: A circuit includes a current controller oscillator generating a CCO output signal at a CCO output, a charge pump boosting a supply voltage based on the CCO output signal and producing a charge pump output voltage at an output, and a current sensing circuit sensing load current at the output and generating a feedback signal having a magnitude that varies with the sensed load current if a magnitude of the sensed load current is between lower and upper load current thresholds. A frequency of the CCO output signal is constant at a lower frequency threshold where the sensed load current is below the lower load current threshold, asymptomically rises to an upper frequency threshold where the sensed load current is above the upper load current threshold, and is proportional to the feedback signal where the sensed load current is between the lower and upper load current thresholds.
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公开(公告)号：US10784876B1
公开(公告)日：2020-09-22
申请号：US16353122
申请日：2019-03-14
Inventor： Sandor Petenyi
Abstract: A charge pump circuit has load driven clock frequency management. The charge pump circuit includes a CCO generating a CCO output signal that has a frequency generally proportional to a feedback current, and a charge pump operated by the CCO output signal and boosting a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sensing circuit senses a load current drawn by the load and generates the feedback current as having a magnitude that varies as a function of the sensed load current if a magnitude of the load current is between a lower load current threshold and an upper load current threshold. The magnitude of the feedback current does not vary with the sensed load current if the magnitude of the sensed load current is not between the lower load current threshold and the upper load current threshold.
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公开(公告)号：US10289140B2
公开(公告)日：2019-05-14
申请号：US15336029
申请日：2016-10-27
Inventor： Sandor Petenyi
Abstract: A voltage regulator having bias current boosting is provided. The voltage regulator includes a power stage for providing an output voltage to a load. The voltage regulator includes a differential stage that receives a feedback voltage representative of the output voltage and a reference voltage and controls the power stage based on a difference between the reference voltage and the feedback voltage. The voltage regulator includes a bias current boosting stage that receives the feedback and reference voltages. The bias current boosting stage provides a boosted bias current having a current level that is based on the difference between the reference and feedback voltages. The boosted bias current biases the differential stage and hastens a response of the differential stage, in response to a change in the difference between the reference voltage and the feedback voltage, in controlling the power stage.
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公开(公告)号：US09785165B2
公开(公告)日：2017-10-10
申请号：US15014320
申请日：2016-02-03
Inventor： Sandor Petenyi , Calogero Ribellino
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: A significant reduction of the amplitude of the transient response is obtained by keeping a low dropout regulator circuit in a closed loop condition. This is achieved by manipulation of the reference voltage level when an open loop condition arises due to a falling input voltage. In this case, the reference voltage level is tracked with the input voltage level, keeping the output voltage regulated. As a consequence, the power pass element of the regulator is not forced into the linear region (in the case of a MOSFET) or deep saturation (in the case of a bipolar transistor).
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