公开(公告)号：US20230231559A1

公开(公告)日：2023-07-20

申请号：US18151337

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Kallol CHATTERJEE ,  Rohit Kumar GUPTA

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.

公开(公告)号：US20230062144A1

公开(公告)日：2023-03-02

申请号：US17898239

申请日：2022-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Namerita KHANNA ,  Rajnish GARG ,  Rohit Kumar GUPTA

IPC: H04L7/033 ,  H03K19/21 ,  H03K3/037

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.

公开(公告)号：US20240396535A1

公开(公告)日：2024-11-28

申请号：US18666532

申请日：2024-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Rohit Kumar GUPTA

IPC: H03K3/037 ,  H03K3/012

Abstract: A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.

公开(公告)号：US20240266343A1

公开(公告)日：2024-08-08

申请号：US18418051

申请日：2024-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Anuj BHARDWAJ ,  Anand Kumar MISHRA ,  Rohit Kumar GUPTA

IPC: H01L27/02 ,  H01L21/762 ,  H01L23/538 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/76224 ,  H01L23/5386 ,  H01L29/0607

Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.