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公开(公告)号：US20220352896A1
公开(公告)日：2022-11-03
申请号：US17863708
申请日：2022-07-13
发明人： Gagan MIDHA , Kallol CHATTERJEE , Anand KUMAR , Ankit GUPTA
摘要： A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
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公开(公告)号：US20210265947A1
公开(公告)日：2021-08-26
申请号：US17175732
申请日：2021-02-15
发明人： Gagan MIDHA , Anurup MITRA , Kallol CHATTERJEE
摘要： Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
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公开(公告)号：US20210135681A1
公开(公告)日：2021-05-06
申请号：US17089090
申请日：2020-11-04
发明人： Gagan MIDHA , Kallol CHATTERJEE
摘要： A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
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公开(公告)号：US20220209777A1
公开(公告)日：2022-06-30
申请号：US17521210
申请日：2021-11-08
发明人： Gagan MIDHA , Kallol CHATTERJEE , Anand KUMAR , Ankit GUPTA
摘要： A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.
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