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    Power measurement circuit
    1.
    发明授权
    Power measurement circuit 有权
    功率测量电路

    公开(公告)号：US09167023B2

    公开(公告)日：2015-10-20

    申请号：US14078118

    申请日：2013-11-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Surinder Pal Singh ,  Kaushik Saha

    IPC: G01R19/18 ,  H04L29/08 ,  G01R21/133 ,  G01R19/22 ,  H04L12/24

    CPC classification number: H04L67/025 ,  G01R19/22 ,  G01R21/133 ,  H04L41/32

    Abstract: A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

    Abstract translation: 电子设备中的功率测量系统包括感测单元，模数转换器（ADC）和控制器。 感测单元感测电源两端的电压，并根据检测到的电压调制载波信号。 ADC转换由电子设备接收的调制载波信号和音频信号的组合，以产生数字化的组合信号，并将数字化的组合信号提供给控制器。 控制器分离数字化调制载波信号和数字化音频信号。 数字化调制载波信号被解调以产生提供电子设备消耗的功率的量度的输出信号。

    Parallelization of variable length decoding
    2.
    发明授权
    Parallelization of variable length decoding 有权
    可变长度解码的并行化

    公开(公告)号：US08942502B2

    公开(公告)日：2015-01-27

    申请号：US13963860

    申请日：2013-08-09

    Applicant: STMicroelectronics International N.V.

    Inventor： Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

    IPC: G06K9/36 ,  G06K9/46 ,  G06T9/00 ,  H03M7/40 ,  H04N19/44 ,  H04N19/436 ,  H04N19/46 ,  H04N19/91

    CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

    Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

    Abstract translation: 用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。 所确定的标记与编码数据一起被包括在编码数据流中。 在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。 编码数据被分成分开并且并行解码的分区。

    Memory manager
    4.
    发明授权
    Memory manager 有权
    内存管理器

    公开(公告)号：US09142322B2

    公开(公告)日：2015-09-22

    申请号：US13964299

    申请日：2013-08-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Deepak Baranwal ,  Digvijay Pratap Singh ,  Kaushik Saha

    IPC: G11C29/00 ,  G11C29/08 ,  G11C29/04

    CPC classification number: G11C29/08 ,  G11C29/04 ,  G11C29/76 ,  G11C2029/0409

    Abstract: An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold.

    Abstract translation: 管理器的实施例包括被配置为接收关于集成电路的区域的信息的至少一个输入节点，以及被配置为响应于该信息确定该区域将导致错误的可能性的确定器。 例如，如果存储器将导致其存储的数据中的错误等于或超过似然阈值的可能性，则该区域可以包括存储器，并且存储器的内容可以被传送到另一个更可靠的存储器。

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