公开(公告)号：US20230062144A1

公开(公告)日：2023-03-02

申请号：US17898239

申请日：2022-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Namerita KHANNA ,  Rajnish GARG ,  Rohit Kumar GUPTA

IPC: H04L7/033 ,  H03K19/21 ,  H03K3/037

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.