公开(公告)号：US12170120B2

公开(公告)日：2024-12-17

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh Chawla ,  Tanuj Kumar ,  Bhupender Singh ,  Harsh Rawat ,  Kedar Janardan Dhori ,  Manuj Ayodhyawasi ,  Nitin Chawla ,  Promod Kumar

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US11025252B2

公开(公告)日：2021-06-01

申请号：US16578487

申请日：2019-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanuj Kumar ,  Deepak Kumar Bihani

IPC: H03K19/003

Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.