公开(公告)号：US11900240B2

公开(公告)日：2024-02-13

申请号：US17023144

申请日：2020-09-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Manuj Ayodhyawasi ,  Thomas Boesch ,  Surinder Pal Singh

IPC: G06N3/06 ,  G06F1/32 ,  G06F9/50 ,  G06F1/08 ,  G06N3/063 ,  G06N3/082 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06N3/063 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/5027 ,  G06N3/082

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：US11984151B2

公开(公告)日：2024-05-14

申请号：US17850207

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

公开(公告)号：US12176025B2

公开(公告)日：2024-12-24

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

公开(公告)号：US12237007B2

公开(公告)日：2025-02-25

申请号：US17852567

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori ,  Harsh Rawat ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

公开(公告)号：US12170120B2

公开(公告)日：2024-12-17

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh Chawla ,  Tanuj Kumar ,  Bhupender Singh ,  Harsh Rawat ,  Kedar Janardan Dhori ,  Manuj Ayodhyawasi ,  Nitin Chawla ,  Promod Kumar

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US11836346B2

公开(公告)日：2023-12-05

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Anuj Grover ,  Thomas Boesch ,  Surinder Pal Singh ,  Manuj Ayodhyawasi

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US12183424B2

公开(公告)日：2024-12-31

申请号：US17954060

申请日：2022-09-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

公开(公告)号：US12087356B2

公开(公告)日：2024-09-10

申请号：US17849903

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/418

CPC classification number: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US11360667B2

公开(公告)日：2022-06-14

申请号：US17012501

申请日：2020-09-04

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Anuj Grover ,  Thomas Boesch ,  Surinder Pal Singh ,  Manuj Ayodhyawasi

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.