公开(公告)号：US20230091970A1

公开(公告)日：2023-03-23

申请号：US18052514

申请日：2022-11-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US20220020754A1

公开(公告)日：2022-01-20

申请号：US17491201

申请日：2021-09-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US20190198508A1

公开(公告)日：2019-06-27

申请号：US16211113

申请日：2018-12-05

Applicant: STMicroelectronics International N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06

CPC classification number: H01L27/1104 ,  G11C5/063 ,  G11C11/412

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.