公开(公告)号：US20030177483A1

公开(公告)日：2003-09-18

申请号：US10099455

申请日：2002-03-14

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F009/44

CPC classification number: G06F12/126 ,  G06F8/54

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract translation: 一种链接多个对象文件以生成可执行程序的方法，所述方法包括在执行程序时在目标文件中识别要被锁定到高速缓存中的至少一个例程，将所述例程定位在一组存储器地址 到一组缓存位置，并将映射到同一组高速缓存位置的其他存储器地址集合引入可执行程序间隙。

公开(公告)号：US20040030839A1

公开(公告)日：2004-02-12

申请号：US10278772

申请日：2002-10-22

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F012/08

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/6026

Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

Abstract translation: 高速缓存存储器包括：提取引擎，被配置为发出用于从正在执行的程序中的访问地址识别的主存储器中的位置访问数据项的提取请求，控制的预取引擎发布用于推测访问预取的预取请求 来自所述主存储器中的位置的数据项，其由被确定为来自所述访问地址的相应位置的位置的数量确定;以及校准器，被配置为选择性地改变所述位置数。

公开(公告)号：US20030154342A1

公开(公告)日：2003-08-14

申请号：US10072814

申请日：2002-02-08

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger ,  Kristen Jacobs

IPC: G06F012/08

CPC classification number: G06F8/4442

Abstract: A memory map evaluation tool is provided which allows a program to be organised in a manner most compatible with use of a cache. This is done by executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract translation: 提供了一种存储器映射评估工具，其允许以与缓存的使用最相容的方式组织程序。 这是通过根据第一存储器映射执行程序的第一版本来完成的，以生成程序计数器跟踪，将程序计数器跟踪转换成特定格式，然后使用要评估的存储器映射将程序计数器跟踪转换为物理地址 ，与第一个存储器映射不同。 然后，这些物理地址用于使用正在评估的内存映射的直接映射高速缓存的模型来评估可能的高速缓存未命中的数量。