公开(公告)号：US20020013876A1

公开(公告)日：2002-01-31

申请号：US09859207

申请日：2001-05-16

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G06F012/00 ,  G11C005/00 ,  G11C029/00

CPC classification number: G06F11/1068 ,  G11C16/10

Abstract: An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

Abstract translation: 电可擦除可编程存储器包括具有连接到字线和位线的存储器单元的存储器阵列。 位线排列成列。 该存储器还包括连接到位线的读取电路和将位线连接到编程线的编程锁存器。 存储器包括当数据已经被加载到列的锁存器中时断开将列的存储单元连接到读取电路的导电路径的装置，而不会破坏将列的锁存器连接到读取电路的导电路径。

公开(公告)号：US20030001659A1

公开(公告)日：2003-01-02

申请号：US10164840

申请日：2002-06-06

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G05F001/10

CPC classification number: G05F3/205 ,  G05F3/262

Abstract: A bias circuit integrated on a silicon wafer includes first, second and third branches. The first branch includes a first PMOS transistor in series with a first NMOS transistor. The second branch includes a second PMOS transistor, a second NMOS transistor and an electric resistor in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The third branch includes a third PMOS transistor in series with a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a drain voltage of the first PMOS transistor that is substantially identical to a drain voltage of the second PMOS transistor.

Abstract translation: 集成在硅晶片上的偏置电路包括第一，第二和第三分支。 第一分支包括与第一NMOS晶体管串联的第一PMOS晶体管。 第二分支包括第二PMOS晶体管，第二NMOS晶体管和串联的电阻器。 第一NMOS晶体管的栅极连接到第二NMOS晶体管的栅极。 第一分支和第二分支被布置为电流镜。 第三分支包括与第三NMOS晶体管串联的第三PMOS晶体管。 第三PMOS和NMOS晶体管布置成保持第一PMOS晶体管的漏极电压基本上等于第二PMOS晶体管的漏极电压。

公开(公告)号：US20020196072A1

公开(公告)日：2002-12-26

申请号：US10164839

申请日：2002-06-06

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G05F001/10

CPC classification number: G05F3/30 ,  G05F3/205 ,  G05F3/262

Abstract: A bias device includes a first branch and a second branch. The first branch includes a first bipolar device and a corresponding bias circuit. The second branch includes a second bipolar device and a corresponding bias circuit. A self-bias circuit is connected to the first and second branches. A first current generator injects a first auxiliary current into the first bipolar device. A second current generator injects a second current into the second bipolar device that is equal or proportional to the first auxiliary current. The bias device stabilizes the operating point of a circuit.

Abstract translation: 偏置装置包括第一分支和第二分支。 第一分支包括第一双极器件和相应的偏置电路。 第二分支包括第二双极器件和相应的偏置电路。 自偏置电路连接到第一和第二分支。 第一电流发生器将第一辅助电流注入第一双极器件。 第二电流发生器将与第一辅助电流相等或成比例的第二电流注入第二双极器件。 偏置装置稳定电路的工作点。