公开(公告)号：US20030147290A1

公开(公告)日：2003-08-07

申请号：US10334126

申请日：2002-12-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C007/00

CPC classification number: G11C11/5621 ,  G11C8/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/30

Abstract: A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

Abstract translation: 电源电路结构对于包含多层存储器单元阵列的集成电可编程/可擦除非易失性存储器件的/从存储单元读/写数据的行解码器是有用的。 有利地，提供了对行解码器的多个电源电压和用于将电压传送到分层模式使能的传导路径的开关电路。

公开(公告)号：US20040208063A1

公开(公告)日：2004-10-21

申请号：US10675221

申请日：2003-09-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34 ,  G11C016/04

CPC classification number: G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

Abstract: The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

Abstract translation: 本发明涉及一种用于擦除非易失性存储单元的方法，以及实现该方法的可编程和电可擦除类型的相应非易失性存储器件，并且包括以行和列布局组织的存储单元阵列， 并且被划分成阵列扇区，包括至少一个行解码电路部分被提供正和负电压。 每当擦除算法的问题为负时，该方法被应用，并且包括以下步骤：强制将未完全擦除的扇区进入读取状态; 扫描所述扇区的行以检查指示故障状态的寄生电流的可能存在; 识别和电隔离失败的行; 从所述故障行重新寻址到在同一扇区中提供的冗余行; 重新启动擦除算法。

公开(公告)号：US20020054504A1

公开(公告)日：2002-05-09

申请号：US09957628

申请日：2001-09-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C016/04

CPC classification number: G11C11/5621 ,  G11C16/0416 ,  G11C2211/5641

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract translation: 多电平存储器件具有存储器部分，该存储器部分包含可以以大于2的预定数量的级别（即，多级阵列）编程的单元，以及包含可以用两个级别编程的单元的存储器部分，即双层阵列。 多级阵列用于存储高密度数据，读取速度不是必需的，例如用于存储包括存储器件的系统的操作代码。 另一方面，双层阵列用于存储读取的高速度和可靠性至关重要的数据，例如个人计算机的BIOS以及要存储在高速缓冲存储器中的数据。 专用于编程，写入测试指令的电路部分以及存储器件操作所需的所有功能对于这两个阵列都是共同的。

公开(公告)号：US20030028709A1

公开(公告)日：2003-02-06

申请号：US10159780

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo ,  Salvatrice Scommegna

IPC: G06F012/00

CPC classification number: G11C16/344 ,  G11C16/3436

Abstract: Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.

Abstract translation: 这里描述了一种用于电可擦除非易失性存储器件，特别是EEPROM闪存非易失性存储器件的擦除方法，其特征在于包括由排列成行和列的多个存储单元形成的存储器阵列， 子行业，其又由一行或多行形成。 存储器阵列的擦除由扇区执行，并且对于每个扇区，设想对扇区的所有存储器单元的栅极端子施加擦除脉冲，验证每个子部件的存储器单元的擦除，以及向栅极施加另外的擦除脉冲 只有子部分的存储器单元的端子不被完全擦除。