公开(公告)号：US20020097071A1

公开(公告)日：2002-07-25

申请号：US10032232

申请日：2001-12-21

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Angelo Nagari ,  Germano Nicollini

IPC: H03B001/00

CPC classification number: G11C7/1051 ,  H03K19/00361

Abstract: The buffer has an output stage formed by two complementary MOS transistors connected so as to operate in phase opposition between the supply terminals and two driver stages having the input in common. Each driver stage has a first branch comprising a current-generator connected between the gate electrode of the transistor to be driven and a supply terminal and an electronic switch controlled by the input and connected between the same gate electrode and the other supply terminal, and a second branch which comprises, connected in series, a transistor connected as a diode and an electronic switch controlled by the output, and is arranged between the gate electrode of the transistor to be driven and a respective supply terminal. The buffer can control a load with a constant switching current, is simple in structure, and occupies a small area.

Abstract translation: 缓冲器具有由两个互补MOS晶体管形成的输出级，所述两个互补MOS晶体管被连接以在电源端子和具有共同输入的两个驱动器级之间相对操作。 每个驱动器级具有第一分支，包括连接在待驱动晶体管的栅电极与供电端子之间的电流发生器和由输入控制并连接在同一栅电极和另一供电端子之间的电子开关， 第二分支，其包括串联连接的二极管的晶体管和由输出控制的电子开关，并且被布置在待驱动的晶体管的栅电极和相应的供电端子之间。 缓冲器可以用恒定的开关电流来控制负载，结构简单，占用面积小。

公开(公告)号：US20040039953A1

公开(公告)日：2004-02-26

申请号：US10460035

申请日：2003-06-10

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Angelo Nagari ,  Germano Nicollini

IPC: G06F001/26 ,  G06F001/32

CPC classification number: H03K17/166 ,  H03K17/164

Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract translation: 数字系统包括数字数据处理单元，连接到处理单元的至少一个输出缓冲器，以响应于从处理单元到达的数字信号产生输出信号，并且至少一个用户单元作为输出缓冲器负载进行连接。 为了确保输出缓冲器的开关电流可以被设置为不同的值，输出缓冲器包括用于将开关电流固定为基本上恒定且与负载无关的值的装置和用于选择性地设置 开关电流和处理单元包括用于存储预定参数的装置; 所述装置连接到选择设定装置，用于将切换电流的值设定为预定参数的函数。

公开(公告)号：US20030231130A1

公开(公告)日：2003-12-18

申请号：US10172376

申请日：2002-06-14

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M001/38 ,  H03M001/10

CPC classification number: H03M1/181 ,  H03M1/468

Abstract: A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.

Abstract translation: 一种操作SAR型模数转换器以匹配要转换的输入电压信号的动态范围与转换器的满量程范围的方法，所述转换器包括至少一个二进制加权电容器阵列。 该方法包括获得数字增益代码的步骤，该数字增益代码表示满量程范围和要转换的电压信号的动态范围之间的比率，将要转换的电压信号施加到电容器阵列，以便对电压进行充电 信号仅转换具有与具有选定二进制值的增益码的位相同的二进制权重的阵列电容器，并且根据SAR选择性地将阵列的电容器耦合到第一和第二预定参考电压端子之一 技术，以获得对应于输入电压信号的输出数字代码。