公开(公告)号：US20040263367A1

公开(公告)日：2004-12-30

申请号：US10641332

申请日：2003-08-14

申请人： Optichron, Inc.

发明人： Roy G. Batruni

IPC分类号： H03M001/10

CPC分类号： H03M1/1061 ,  H03M1/0614 ,  H03M1/145

摘要： A system and method are disclosed for correcting for output distortion of an analog to digital converter, comprising: estimating the output distortion, providing an estimated distortion, and combining an output of the analog to digital converter with the estimated distortion to compensate for the output distortion. The compensating module for correcting output distortion of an analog to digital converter comprises a calibration module configured to estimate the output distortion and a combiner configured to combine an output of the analog to digital converter with the estimated distortion to compensate the output distortion.

摘要翻译： 公开了一种用于校正模数转换器的输出失真的系统和方法，包括：估计输出失真，提供估计的失真，以及将所述模数转换器的输出与估计的失真相结合以补偿输出失真 。 用于校正模数转换器的输出失真的补偿模块包括被配置为估计输出失真的校准模块和被配置为将模数转换器的输出与所估计的失真组合以补偿输出失真的组合器。

公开(公告)号：US20030184466A1

公开(公告)日：2003-10-02

申请号：US10268157

申请日：2002-10-10

发明人： Masato Takeyabu ,  Yuji Kobayashi

IPC分类号： H03M001/12 ,  H03M001/10 ,  H03M001/38

CPC分类号： H03M1/1061 ,  H03M1/442

摘要： The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

摘要翻译： 本发明涉及包括具有流水线配置的多个级的模拟转换单元和数字转换单元的模拟/数字转换器。 数字转换单元具有数字值存储寄存器，每个存储寄存器分别用于其中一个级。 每个寄存器用于存储每个段的数字值完成错误校正，并且适于输出对应于段号的数字值。 数字转换单元还具有误差计算控制单元，其控制级，使得特定一级输入误差计算模拟信号。 然后，误差计算控制单元基于从与特定级之后的所有级接收到的段号对应的数字值计算出的数字转换数据，计算出特定级的误差。

公开(公告)号：US20030184461A1

公开(公告)日：2003-10-02

申请号：US10114165

申请日：2002-04-02

发明人： William R. Goyette ,  Harry S. Harberts

IPC分类号： H03M001/10 ,  H03L005/00

CPC分类号： H03H7/255 ,  H03G1/0058

摘要： A differential PIN diode attenuator (450) that selectively attenuates a differential analog input signal. The two parts of the differential signal are applied to separate input lines (452, 454) and are 180null out of phase with each other. One input line (452) is coupled to a first attenuation path (456) including a resistor and a first non-attenuation path (458) including a PIN diode (462). The other input line (454) is coupled to a second attenuation path (466) including a resistor and a second non-attenuation path (468) including a PIN diode (472). The diodes (462, 472) are biased by a DC bias signal so that the differential analog signal can bypass the attenuation paths (456, 466). The DC bias signal is applied halfway between the input lines (452, 454) where the two parts of the differential signal cancel. A shunt diode (490, 492,) and parallel shunt resistors are provided in combination with the attenuation resistor to allow it to have a relatively small value.

摘要翻译： 差分PIN二极管衰减器（450），其选择性地衰减差分模拟输入信号。 差分信号的两个部分被施加到分离的输入线（452,454）并且彼此相位相差180°。 一个输入线（452）耦合到包括电阻器的第一衰减路径（456）和包括PIN二极管（462）的第一非衰减路径（458）。 另一个输入线（454）耦合到包括电阻器的第二衰减路径（466）和包括PIN二极管（472）的第二非衰减路径（468）。 二极管（462,472）被DC偏置信号偏置，使差分模拟信号可以绕过衰减路径（456,466）。 DC偏置信号被施加在差分信号的两个部分取消的输入线（452,454）之间的中途。 与衰减电阻器组合提供并联二极管（490,492）和并联分流电阻器，以使其具有相对较小的值。

公开(公告)号：US20030160713A1

公开(公告)日：2003-08-28

申请号：US10063509

申请日：2002-05-01

申请人： Texas Instruments Incorporated

发明人： Turker Kuyel ,  Kumar Lakshmi Parthasarathy

IPC分类号： H03M001/10

CPC分类号： H03M1/1047 ,  H03M1/76

摘要： A calibrated digital-to-analog converter (DAC) (15null) has a main DAC (17) having a digital input and an analog output. An on-chip memory (21) stores measured INL values of the main DAC at a few selected input codes, and digital interpolation (50,17) is used to approximate INL error values at all input codes (14 . . . 14Vl). To cancel the INL errors of the main DAC, outputs of this digital interpolation are sent to a calibration DAC (19), which has an analog output subtracted from the analog output of the main DAC. This subtraction can also be done in the digital domain, removing the need for a calibration-DAC when a main DAC with higher bit-count is designed.

摘要翻译： 校准的数模转换器（DAC）（15'）具有具有数字输入和模拟输出的主DAC（17）。 片上存储器（21）将测量的主DAC的INL值存储在几个选择的输入代码处，并且数字内插（50,17）用于在所有输入代码（14 ... 14V1）处近似INL误差值。 要取消主DAC的INL错误，该数字内插的输出将发送到校准DAC（19），该DAC（19）具有从主DAC的模拟输出中减去的模拟输出。 这种减法也可以在数字领域完成，当设计具有较高位数的主DAC时，无需校准DAC。

公开(公告)号：US20030146863A1

公开(公告)日：2003-08-07

申请号：US10372138

申请日：2003-02-25

发明人： Bengt Erik Jonsson

IPC分类号： H03M001/10

CPC分类号： H03M1/1004 ,  H03M1/12

摘要： An A/D converter calibration apparatus includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1, . . . , xN. The measured parameters are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds a predetermined change threshold. When a change exceeding the threshold has been detected, a calibration trigger signal CAL_TRIG is passed to a calibration control unit (104), which initiates a background calibration sequence.

摘要翻译： A / D转换器校准装置包括用于检测由参数x1表示的当前操作条件的一组操作条件参数传感器（100）。 。 。 ，xN。 将测量的参数转发到操作条件变化检测器（102），该检测器计算变化量度并确定该测量值是否超过预定的变化阈值。 当检测到超过阈值的变化时，校准触发信号CAL_TRIG被传递到校准控制单元（104），其启动背景校准序列。

公开(公告)号：US20020180626A1

公开(公告)日：2002-12-05

申请号：US10127197

申请日：2002-04-19

申请人： ROHM CO., LTD.

发明人： Jun Sasaki ,  Yasunori Kawamura

IPC分类号： H03M001/10

CPC分类号： H03M1/108 ,  H03M1/66

摘要： A semiconductor device equipped with a DAC channel has a test pattern generation means for storing and generating test patters, and a test clock input terminal. The test pattern generation means generates a test digital signal representing a test pattern based on the high-frequency (e.g. 135 MHz) test clock input to the test clock input terminal. The test digital signal is supplied to the input end of the DAC channel. Using the test digital signals supplied from the test signal generation means, the semiconductor device can be tested in various high-frequency test modes without any tester outputting high-frequency test signals.

摘要翻译： 配备有DAC通道的半导体器件具有用于存储和产生测试图案的测试图形生成装置和测试时钟输入端子。 测试图形生成装置基于输入到测试时钟输入端子的高频（例如135MHz）测试时钟产生表示测试图形的测试数字信号。 测试数字信号被提供给DAC通道的输入端。 使用从测试信号发生装置提供的测试数字信号，可以在各种高频测试模式下测试半导体器件，而不需要任何测试仪输出高频测试信号。

公开(公告)号：US20020171569A1

公开(公告)日：2002-11-21

申请号：US09820801

申请日：2001-03-30

发明人： Weibiao Zhang ,  Marwan Hassoun

IPC分类号： H03M001/10 ,  H03M001/06

CPC分类号： H03M1/1061 ,  H03M1/747

摘要： In accordance with a preferred embodiment, a self-calibrated cell (and corresponding operation) is provided that receives a reference parameter (e.g., current, voltage, etc.) for storage in the cell and for supplying to a load. The individual cell is controlled to operate in different states or modes: either a redundant mode or a supplying mode. In the redundant mode, the reference parameter is stored in the current cell during a calibration phase or mode, and the stored reference parameter is dumped or otherwise transferred, preferably to ground, during a dumping state or mode. In the supplying mode, the current cell transfers or supplies the stored reference parameter to the load. The individual cell is controlled to operate in its dumping state both before the cell enters the calibration mode and also at the same time that the cell is switched from the calibration mode to the supplying mode. In accordance with a preferred embodiment, the individual cells may be employed in a cell array of a converter (e.g., digital-to-analog converter). All of the cells in the array may individually be placed in a redundant mode in succession, while the remaining cells are in a supplying mode.

摘要翻译： 根据优选实施例，提供自校准单元（以及对应的操作），其接收参考参数（例如，电流，电压等）以存储在单元中并供给负载。 控制单个电池以不同的状态或模式工作：冗余模式或供电模式。 在冗余模式下，在校准阶段或模式期间，参考参数存储在当前单元中，并且在倾倒状态或模式期间将存储的参考参数倾倒或以其它方式转移，优选地接地。 在供电模式下，当前单元将所存储的参考参数传送或提供给负载。 控制单个电池在电池进入校准模式之前以及在电池从校准模式切换到供电模式的同时在其倾卸状态下操作。 根据优选实施例，各个单元可以用于转换器的单元阵列（例如，数模转换器）。 阵列中的所有单元格可以单独地以冗余模式连续放置，而剩余的单元格处于供电模式。

公开(公告)号：US20020030616A1

公开(公告)日：2002-03-14

申请号：US09891788

申请日：2001-06-26

发明人： Tomonobu Hiramatsu ,  Shinichi Tanida

IPC分类号： H03M001/10

CPC分类号： H03M1/10 ,  H03M1/12

摘要： In order to shorten the measuring time of an analog-digital converter for measuring very small currents with its resolution unchanged, a method of determining the measuring time for the analog-digital converter which comprises the steps of preliminarily measuring current to be measured, determining a voltage range and a current range used for measurement, and determining the measuring time for an analog-digital converter for current measurement on the basis of the determined voltage and current ranges, and the measured current value is provided.

摘要翻译： 为了缩短用于测量其分辨率不变的非常小的电流的模拟数字转换器的测量时间，确定模数转换器的测量时间的方法包括以下步骤：初步测量要测量的电流，确定 电压范围和用于测量的电流范围，并且基于所确定的电压和电流范围确定用于电流测量的模数转换器的测量时间，并且提供测量的电流值。

公开(公告)号：US20020030615A1

公开(公告)日：2002-03-14

申请号：US09838359

申请日：2001-04-19

发明人： Sasikumar Cherubal ,  Abhijit Chatterjee

IPC分类号： H03M001/10

CPC分类号： H03M1/109 ,  H03M1/12

摘要： A method and system for making optimal estimates of linearity metrics of analog-to-digital converters. A model building phase and a production test strategy are employed. During the model-building phase, a linear model an analog-to-digital converter is constructed from a set of accurately measured transition code voltages for a set of training analog-to-digital converters. During a production test of an individual analog-to-digital converter, a ramp test signal is applied to the individual analog-to-digital converter, a histogram of codes is produced, and the transition code voltages for the individual analog-to-digital converter are estimated from the resulting histogram. Linearity characteristics of the individual analog-to-digital converter may then be computed.

公开(公告)号：US20040246155A1

公开(公告)日：2004-12-09

申请号：US10860022

申请日：2004-06-04

发明人： Chen-Chih Huang

IPC分类号： H03M001/10 ,  H03M001/66

CPC分类号： H03M1/0673 ,  H03M1/662

摘要： A digital to analog converter (DAC) converts a plurality of digital input data into a plurality of analog output signals. The DAC includes an element pool having a plurality of elements, a random number generator for converting the digital input data into a set of control signals, a plurality of summing nodes for generating analog output signals, and a plurality of switches for connecting the elements to the summing nodes. The switches are controlled by the control signals. Because of the control of the random number generator, the element signals transferring to the summing nodes can be used alternatively and simultaneously.

摘要翻译： 数模转换器（DAC）将多个数字输入数据转换为多个模拟输出信号。 DAC包括具有多个元件的元件池，用于将数字输入数据转换为一组控制信号的随机数发生器，用于产生模拟输出信号的多个求和节点和用于将元件连接到 求和节点。 开关由控制信号控制。 由于随机数发生器的控制，可以交替地和同时地使用传递到求和节点的元素信号。