公开(公告)号：US20030182533A1

公开(公告)日：2003-09-25

申请号：US10371221

申请日：2003-02-21

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Poli ,  Paolino Schillaci ,  Salvatore Polizzi

IPC: G06F012/00 ,  G06F012/14

CPC classification number: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract translation: 本发明提供了一种协议周期，在该协议周期期间，发送存储器地址和要写入的所有数据字节，并且通过在对应于一个存储器区域的存储器扇区中写入第一个字节，对所有发送的数据字节仅执行一次写入处理 通过将所发送的地址的2个最低有效位和连续地址中的所有其他发送字节重置为零而产生的第一地址。 该方法包括在存储器件的存储器阵列中的连续存储器地址中写入一定数量的N个数据字节，并且包括不保护要写入数据的存储器扇区，将编程命令传送到存储器件，与 存储器件将要存储的位并指定要写入的扇区的相对存储器地址，以及将数据位写入存储器。

公开(公告)号：US20040083327A1

公开(公告)日：2004-04-29

申请号：US10623474

申请日：2003-07-18

Applicant: STMicroelectronics S.r.I.

Inventor： Paolino Schillaci ,  Salvatore Poli ,  Antonino La Malfa

IPC: G06F012/00

CPC classification number: G11C8/06 ,  G06F12/0653 ,  G11C15/00

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Abstract translation: 本发明涉及一种用于映射和选择在主板上的可用寻址区域中具有LPC串行通信接口的非易失性存储器件的自动解码方法。 逻辑结构被结合在存储器件中，其允许正确的解码将存储器寻址到可寻址区域的顶部或相同区域的底部，即在两种可能的情况下。 该逻辑包含非易失性寄存器，其信息存储在内容地址存储器中，以使得可寻址存储器区域中的存储器自动映射。

公开(公告)号：US20030088729A1

公开(公告)日：2003-05-08

申请号：US10271352

申请日：2002-10-15

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Polizzi ,  Salvatore Poli ,  Maurizio Perroni

IPC: G06F012/00

CPC classification number: G11C7/1075 ,  G11C16/08 ,  G11C16/26 ,  G11C2207/107 ,  G11C2216/30

Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

Abstract translation: 非易失性存储器件可以串行模式和并行模式工作。 非易失性存储器件的架构基于已经存在于标准存储器中的结构，但是包括某些修改。 这些修改包括为各种存储器访问阶段（即，写入和读取数据）添加定时状态机，以及添加内部总线和相关逻辑电路，用于在非易失性存储器中禁用标准存储器的内部地址总线 设备以串行模式运行。