公开(公告)号：US20030123306A1

公开(公告)日：2003-07-03

申请号：US10325486

申请日：2002-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Polizzi ,  Maurizio Perroni

IPC: G11C007/00

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2281

Abstract: The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal. The array receives data from the state machine through the second internal bus and provides the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slave flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device includes a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

Abstract translation: 本发明的存储器件在从外部时钟的上升沿开始的时间内比其它已知器件的存储器件输出读出的数据，因为输出缓冲器具有通过触发器同步的主 - 从对的阵列 从内部时钟信号导出的各个定时信号。 该阵列通过第二个内部总线从状态机接收数据，并将数据输出到由状态机启用的缓冲区的输出级。 逻辑电路产生主从触发器的定时信号，分别作为状态机产生的内部时钟信号和缓冲器的输出级的使能信号的逻辑“与”和逻辑“与”。 此外，存储器件包括由内部时钟信号同步的电路，其引入与内部时钟信号的周期相当的缓冲器的输出级的使能信号的延迟。

公开(公告)号：US20030088729A1

公开(公告)日：2003-05-08

申请号：US10271352

申请日：2002-10-15

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Polizzi ,  Salvatore Poli ,  Maurizio Perroni

IPC: G06F012/00

CPC classification number: G11C7/1075 ,  G11C16/08 ,  G11C16/26 ,  G11C2207/107 ,  G11C2216/30

Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

Abstract translation: 非易失性存储器件可以串行模式和并行模式工作。 非易失性存储器件的架构基于已经存在于标准存储器中的结构，但是包括某些修改。 这些修改包括为各种存储器访问阶段（即，写入和读取数据）添加定时状态机，以及添加内部总线和相关逻辑电路，用于在非易失性存储器中禁用标准存储器的内部地址总线 设备以串行模式运行。

公开(公告)号：US20030182533A1

公开(公告)日：2003-09-25

申请号：US10371221

申请日：2003-02-21

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Poli ,  Paolino Schillaci ,  Salvatore Polizzi

IPC: G06F012/00 ,  G06F012/14

CPC classification number: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract translation: 本发明提供了一种协议周期，在该协议周期期间，发送存储器地址和要写入的所有数据字节，并且通过在对应于一个存储器区域的存储器扇区中写入第一个字节，对所有发送的数据字节仅执行一次写入处理 通过将所发送的地址的2个最低有效位和连续地址中的所有其他发送字节重置为零而产生的第一地址。 该方法包括在存储器件的存储器阵列中的连续存储器地址中写入一定数量的N个数据字节，并且包括不保护要写入数据的存储器扇区，将编程命令传送到存储器件，与 存储器件将要存储的位并指定要写入的扇区的相对存储器地址，以及将数据位写入存储器。

公开(公告)号：US20030059046A1

公开(公告)日：2003-03-27

申请号：US10199965

申请日：2002-07-18

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Messina ,  Salvatore Polizzi ,  Giulio Mangione

IPC: H04L009/00

CPC classification number: H04L9/0662 ,  H04L2209/12 ,  H04L2209/26

Abstract: A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.

Abstract translation: 描述了用于实现随机数生成器的混合架构，其包括能够提供随机字节序列的数字电路部分以及能够提供真随机类型的种子的模拟电路部分。