公开(公告)号：US20040058493A1

公开(公告)日：2004-03-25

申请号：US10621262

申请日：2003-07-15

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics S.A.

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US20030234413A1

公开(公告)日：2003-12-25

申请号：US10414252

申请日：2003-04-14

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Sberno ,  Salvatore Torrisi ,  Nicolas Demange

IPC: H01L029/76

CPC classification number: G11C7/18 ,  G11C11/22 ,  G11C2211/4013

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

Abstract translation: 铁电半导体存储器包括包括至少一行存储器单元的存储器单元的布置。 至少一行的存储器单元与该布置的相应字线相关联。 存储单元的布置包括从与至少一行相关联的字线分支的多个本地字线，每个本地字线连接到线路的相应组的存储器单元。 选择性连接装置允许选择性地将本地字线之一连接到相应的字线。 存储单元的布置还包括多个局部板偏置线，每个板偏置线与相应组的存储单元相关联，用于选择性地驱动各组的存储单元。