公开(公告)号：US20040058493A1

公开(公告)日：2004-03-25

申请号：US10621262

申请日：2003-07-15

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics S.A.

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US20020050627A1

公开(公告)日：2002-05-02

申请号：US10033508

申请日：2001-12-28

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: H01L029/00

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract translation: 提供集成在半导体层上的用于半导体器件的接触结构。 该结构包括至少一个MOS器件和至少一个电容器元件，其中触点设置在形成在至少部分半导体层的绝缘层中的开口处。 此外，开口具有其表面边缘，壁和底部涂覆有金属层并且填充有绝缘层。

公开(公告)号：US20030082873A1

公开(公告)日：2003-05-01

申请号：US10263361

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: H01L021/8234

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

公开(公告)号：US20030146460A1

公开(公告)日：2003-08-07

申请号：US10327704

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I

Inventor： Raffaele Zambrano ,  Cesare Artoni

IPC: G11C007/00 ,  G11C029/00 ,  H01L029/76 ,  H01L029/94 ,  H01L027/108

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract translation: 堆叠型存储单元由MOS晶体管和铁电电容器形成。 MOS晶体管形成在半导体材料的衬底的有源区中，并且包括导电区域。 铁电电容器形成在有源区的顶部，并且包括由铁电区域分开的第一和第二电极。 接触区域将MOS晶体管的导电区域与铁电体电容器的第一电极连接。 铁电电容器具有非水平部分形成的非平面结构，该水平部分横向于与水平部分直接电接触延伸的两个侧部。

公开(公告)号：US20040175927A1

公开(公告)日：2004-09-09

申请号：US10804492

申请日：2004-03-18

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano ,  Cesare Artoni ,  Chiara Corvasce

IPC: H01L021/4763

CPC classification number: H01L27/11502 ,  H01L21/76877

Abstract: A process forms an integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract translation: 一种方法形成一种集成装置，其具有：第一导电区域; 第二导电区域; 布置在第一和第二导电区域之间的绝缘层; 至少一个通孔，其延伸在所述第一和第二导电区域之间的绝缘层中; 以及形成在所述通孔中并且电连接所述第一导电区域和所述第二导电区域的接触结构。 接触结构由覆盖通孔的侧表面和底部的导电材料层形成，并且包围由第二导电区域封闭在顶部的空区域。 导电材料层优选地包括彼此顶部布置的钛层和氮化钛层。

公开(公告)号：US20030174531A1

公开(公告)日：2003-09-18

申请号：US10360840

申请日：2003-02-07

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: G11C011/22

CPC classification number: G11C11/005

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

Abstract translation: 一种集成装置，包括具有非易失型第一存储单元的第一存储器阵列和具有易失型（DRAM）的第二存储单元的第二存储器阵列。 第一存储单元和第二存储单元形成在半导体材料的衬底中，并且每个包括形成在衬底的有源区中的各自的MOS晶体管，并且具有形成在顶部的第一导电区域和相应的电容器 并且具有由电介质区域分离的第一电极和第二电极。 此外，电容器的第一电极连接到MOS晶体管的第一导电区域。 第一和第二存储单元具有基本上相同并且同时形成的结构。

公开(公告)号：US20020070397A1

公开(公告)日：2002-06-13

申请号：US09998602

申请日：2001-11-16

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: H01L029/94

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A contact structure for a ferroelectric memory device 13 integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the latter, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises at least a plurality of plugs filled with a nonconductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material for the second conduction terminals or the control circuitry.

Abstract translation: 一种集成在半导体衬底中的铁电存储器件13的接触结构，包括适当的控制电路和铁电存储器单元的矩阵阵列，其中每个单元包括连接到铁电电容器的MOS器件。 MOS器件具有第一和第二导电端子并被绝缘层覆盖。 铁电电容器具有形成在第一导电端子上方的绝缘层上的下板，并且与下一个电极电连接，该下板被一层铁电材料覆盖并电容耦合到上板。 有利地，接触结构包括在第一导电端子和铁电电容器之间填充有非导电材料的至少多个插塞，并且包括填充有用于第二导电端子或控制电路的导电材料的多个插头。