公开(公告)号：US20210193658A1

公开(公告)日：2021-06-24

申请号：US17124671

申请日：2020-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea PALEARI ,  Simone Dario MARIANI ,  Irene BALDI ,  Daniela BRAZZELLI ,  Alessandra Piera MERLINI

IPC: H01L27/092 ,  H01L21/762

Abstract: An integrated device includes a deep plug. The deep plug is formed by a deep trench extending in a semiconductor body from a shallow surface of a shallow trench isolation. A trench contact makes contact with a conductive filler of the deep trench through the shallow trench at its shallow surface. A system includes at least one integrated device with the deep plug. Moreover, a corresponding process for manufacturing this integrated device includes steps for forming and filling the deep trench before forming the shallow trench isolation and trench window through which the trench contact extends to make contact with the conductive filler. The semiconductor body has a thickness, and the deep trench extends into the semiconductor body less than the thickness.

公开(公告)号：US20240038604A1

公开(公告)日：2024-02-01

申请号：US18224805

申请日：2023-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Luca CECCHETTO ,  Alessandra Piera MERLINI ,  Gabriella ADDESA

IPC: H01L21/66 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L22/32 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76877

Abstract: A semiconductor chip has a top metal layer with a passivation over an outer surface and including a first region and a second region. The passivation is fully removed from the first region and a contact layer for electrical wafer sorting probes is formed over the first region having the passivation fully removed therefrom. The passivation is initially only partly removed from the second region to protect the top met layer. Later, a remaining portion of the passivation is fully removed at the second region. Then, top metal layer at the second region provides a growth region for growing electrically conductive material over the second region.