公开(公告)号：US20210193658A1

公开(公告)日：2021-06-24

申请号：US17124671

申请日：2020-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea PALEARI ,  Simone Dario MARIANI ,  Irene BALDI ,  Daniela BRAZZELLI ,  Alessandra Piera MERLINI

IPC: H01L27/092 ,  H01L21/762

Abstract: An integrated device includes a deep plug. The deep plug is formed by a deep trench extending in a semiconductor body from a shallow surface of a shallow trench isolation. A trench contact makes contact with a conductive filler of the deep trench through the shallow trench at its shallow surface. A system includes at least one integrated device with the deep plug. Moreover, a corresponding process for manufacturing this integrated device includes steps for forming and filling the deep trench before forming the shallow trench isolation and trench window through which the trench contact extends to make contact with the conductive filler. The semiconductor body has a thickness, and the deep trench extends into the semiconductor body less than the thickness.

公开(公告)号：US20140027837A1

公开(公告)日：2014-01-30

申请号：US13944727

申请日：2013-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea PALEARI ,  Giuseppe CROCE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/743 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7825

Abstract: An embodiment of a MOS transistor includes a layer of semiconductor material, drain regions having a first conductivity type alternately formed in the layer with body regions having a second conductivity type, a first insulating layer disposed over the surface of the layer of semiconductor material, at least one gate-precursor region of conductive material disposed over the first insulating layer, a second insulating layer disposed over the first insulating layer and the gate-precursor region, a third insulating layer disposed over the second insulating layer, at least one source opening formed by removing overlapping portions of the second insulating layer, the third insulating layer, the gate-precursor region, and by at least partially removing a corresponding portion of the first insulating layer. The embodiment may also include at least one source-precursor region extending into the layer of semiconductor material from a surface portion below the at least one source opening.

Abstract translation: MOS晶体管的实施例包括半导体材料层，具有交替形成在具有第二导电类型的主体区域的层中的第一导电类型的漏极区域，设置在半导体材料层的表面上的第一绝缘层， 设置在所述第一绝缘层上的至少一个导电材料的栅极 - 前体区域，设置在所述第一绝缘层和所述栅极 - 前体区域之上的第二绝缘层，设置在所述第二绝缘层上的第三绝缘层，形成的至少一个源极开口 通过去除第二绝缘层，第三绝缘层，栅极 - 前体区域的重叠部分，并且至少部分去除第一绝缘层的相应部分。 该实施例还可以包括从至少一个源极开口下方的表面部分延伸到半导体材料层中的至少一个源极 - 前体区域。