公开(公告)号：US11282573B2

公开(公告)日：2022-03-22

申请号：US16904869

申请日：2020-06-18

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Manfre′ ,  Laura Capecchi ,  Marcella Carissimi ,  Marco Pasotti

IPC: G11C11/00 ,  G11C13/00

Abstract: A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.

公开(公告)号：US10522220B2

公开(公告)日：2019-12-31

申请号：US16056818

申请日：2018-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfre′

IPC: G11C11/00 ,  G11C13/00

Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.

公开(公告)号：US10115460B2

公开(公告)日：2018-10-30

申请号：US15639540

申请日：2017-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfre′ ,  Massimo Fidone

IPC: G11C13/00 ,  G11C8/08 ,  H01L27/24 ,  H01L29/78 ,  H01L45/00

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.