公开(公告)号：US10115460B2

公开(公告)日：2018-10-30

申请号：US15639540

申请日：2017-06-30

申请人： STMicroelectronics S.r.l.

发明人： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfre′ ,  Massimo Fidone

IPC分类号： G11C13/00 ,  G11C8/08 ,  H01L27/24 ,  H01L29/78 ,  H01L45/00

摘要： A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

公开(公告)号：US20180151223A1

公开(公告)日：2018-05-31

申请号：US15639540

申请日：2017-06-30

申请人： STMicroelectronics S.r.l.

发明人： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfre' ,  Massimo Fidone

IPC分类号： G11C13/00 ,  H01L27/24

CPC分类号： G11C13/0028 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/06

摘要： A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

公开(公告)号：US10658032B2

公开(公告)日：2020-05-19

申请号：US16155659

申请日：2018-10-09

申请人： STMicroelectronics S.r.l.

发明人： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfré ,  Massimo Fidone

IPC分类号： G11C13/00 ,  G11C8/08 ,  H01L27/24 ,  G11C5/14 ,  H01L29/78 ,  H01L45/00

摘要： A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

公开(公告)号：US20190043574A1

公开(公告)日：2019-02-07

申请号：US16155659

申请日：2018-10-09

申请人： STMicroelectronics S.r.l.

发明人： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfré ,  Massimo Fidone

IPC分类号： G11C13/00 ,  H01L27/24 ,  G11C8/08 ,  H01L29/78 ,  H01L45/00

摘要： A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.