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公开(公告)号：US12046987B2
公开(公告)日：2024-07-23
申请号：US17582431
申请日：2022-01-24
CPC分类号： H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US11615820B1
公开(公告)日：2023-03-28
申请号：US17490976
申请日：2021-09-30
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US11798603B2
公开(公告)日：2023-10-24
申请号：US18175375
申请日：2023-02-27
发明人： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC分类号： G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
CPC分类号： G11C7/12 , G11C7/065 , G11C7/222 , G11C11/4091 , G11C11/4094
摘要： A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US11615823B2
公开(公告)日：2023-03-28
申请号：US17542203
申请日：2021-12-03
发明人： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC分类号： G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
摘要： A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
IPC分类号： G11C13/00 , G11C16/10 , G11C7/06 , G11C16/08 , G11C16/24 , G11C16/28 , G11C16/30 , G11C16/32
摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US11798630B2
公开(公告)日：2023-10-24
申请号：US17407903
申请日：2021-08-20
发明人： Marcella Carissimi , Fabio Enrico Carlo Disegni , Chantal Auricchio , Cesare Torti , Davide Manfre' , Laura Capecchi , Emanuela Calvetti , Stefano Zanchi
CPC分类号： G11C16/102 , G11C7/04 , G11C16/24 , G11C16/28 , G11C16/30
摘要： A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
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公开(公告)号：US11205462B2
公开(公告)日：2021-12-21
申请号：US17010704
申请日：2020-09-02
发明人： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC分类号： G11C7/10 , G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
摘要： A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US11189343B2
公开(公告)日：2021-11-30
申请号：US16940837
申请日：2020-07-28
摘要： A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.
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公开(公告)号：US11133064B2
公开(公告)日：2021-09-28
申请号：US16931335
申请日：2020-07-16
摘要： A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.
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公开(公告)号：US09921598B1
公开(公告)日：2018-03-20
申请号：US15397137
申请日：2017-01-03
发明人： Marco Pasotti , Laura Capecchi , Riccardo Zurla
CPC分类号： G05F3/26
摘要： A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to supply voltage node. The gates of the input and output transistor are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at a mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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