公开(公告)号：US20200278420A1

公开(公告)日：2020-09-03

申请号：US16795977

申请日：2020-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe PAPOTTO ,  Egidio RAGONESE ,  Claudio NOCERA ,  Alessandro FINOCCHIARO ,  Giuseppe PALMISANO

IPC: G01S7/03 ,  H03F3/19 ,  H03F1/56 ,  H03D7/14

Abstract: An input receives a radio frequency (RF) signal having an interfering component superimposed thereon. The RF signal is mixed with a local oscillator (LO) signal and down-converted to an intermediate frequency (IF) to generate a mixed signal which includes a frequency down-converted interfering component. The mixed signal is amplified by an amplifier to generate an output signal. A feedback loop processes the output signal to generate a correction signal for cancelling the frequency down-converted interfering component at the input of the amplifier. The feedback loop includes a low-pass filter and a amplification circuit which outputs the correction signal.

公开(公告)号：US20240151844A1

公开(公告)日：2024-05-09

申请号：US18418298

申请日：2024-01-21

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro PARISI ,  Andrea CAVARRA ,  Alessandro FINOCCHIARO ,  Giuseppe PAPOTTO ,  Giuseppe PALMISANO

IPC: G01S13/58 ,  G01S7/40 ,  G01S13/931 ,  H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H03L7/193

CPC classification number: G01S13/584 ,  G01S7/4056 ,  G01S13/931 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03L7/099 ,  H03L7/101 ,  H03L7/103 ,  H03L7/193

Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

公开(公告)号：US20160094256A1

公开(公告)日：2016-03-31

申请号：US14751470

申请日：2015-06-26

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Giuseppe PAPOTTO ,  Giuseppe Palmisano

IPC: H04B1/16 ,  H04L27/36 ,  H04W56/00

CPC classification number: H04B1/16 ,  H03F3/24 ,  H03K5/1565 ,  H04L27/364 ,  H04W56/0035 ,  H04W56/005

Abstract: A system for correction of the phase error in in-phase and quadrature signals may include a first signal and a second signal. The system includes a first circuit and a second circuit, each circuit configured for receiving a square-wave input signal and supplying a respective square-wave output signal. The output signal is delayed with respect to the input signal and each circuit is configured in such a way that the propagation delay of a rising edge and the propagation delay of a falling edge between the input signal and the output signal are configurable. The first circuit is configured for receiving the first signal, and the second circuit is configured for receiving the second signal.

Abstract translation: 用于校正同相和正交信号中的相位误差的系统可以包括第一信号和第二信号。 该系统包括第一电路和第二电路，每个电路被配置为接收方波输入信号并提供相应的方波输出信号。 输出信号相对于输入信号被延迟，并且每个电路被配置成使得输入信号和输出信号之间的上升沿的传播延迟和下降沿的传播延迟是可配置的。 第一电路被配置为接收第一信号，并且第二电路被配置为接收第二信号。

公开(公告)号：US20230194694A1

公开(公告)日：2023-06-22

申请号：US18108993

申请日：2023-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro PARISI ,  Andrea CAVARRA ,  Alessandro FINOCCHIARO ,  Giuseppe PAPOTTO ,  Giuseppe PALMISANO

IPC: G01S13/58 ,  G01S7/40 ,  G01S13/931 ,  H03B5/12 ,  H03L7/193 ,  H03L7/099 ,  H03L7/10

CPC classification number: G01S13/584 ,  G01S7/4056 ,  G01S13/931 ,  H03B5/1212 ,  H03B5/1228 ,  H03L7/193 ,  H03B5/1265 ,  H03B5/1293 ,  H03L7/099 ,  H03L7/101 ,  H03L7/103 ,  H03B5/1243

Abstract: Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.

公开(公告)号：US20200266781A1

公开(公告)日：2020-08-20

申请号：US16793144

申请日：2020-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro FINOCCHIARO ,  Giuseppe PAPOTTO ,  Egidio RAGONESE ,  Giuseppe PALMISANO

IPC: H03F3/45 ,  H03F1/34 ,  H04B1/40 ,  B60R11/02 ,  B60R11/04 ,  B60R16/023

Abstract: A cascade of amplifier stages has a differential input and a differential output. The cascade of amplifier stages includes at least one differential amplifier circuit including first and second transistors, at least one of the first and second transistors having a control terminal and a body terminal. A mismatch between the first and second transistors generates an input offset. A feedback network couples the differential output to the body terminal in order to cancel the input offset. The feedback network includes a low-pass filter and a differential amplifier stage.

公开(公告)号：US20240210550A1

公开(公告)日：2024-06-27

申请号：US18594456

申请日：2024-03-04

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro FINOCCHIARO ,  Alessandro PARISI ,  Andrea CAVARRA ,  Giuseppe PAPOTTO ,  Giuseppe PALMISANO

IPC: G01S13/34 ,  G01S13/931 ,  H03B5/12 ,  H03L7/193

CPC classification number: G01S13/34 ,  G01S13/931 ,  H03B5/1231 ,  H03L7/193

Abstract: A circuit includes a phase-frequency-detector generating first and second digital control signals indicative of phase differences between an input reference-signal and an output-signal, a charge-pump generating a control-signal based upon the first and second digital control signals, and an oscillator-circuit. The oscillator-circuit includes an active core coupled between first and second nodes, with a tunable resonant circuit a set of capacitances selectively connected between the first and second nodes, wherein a tap between the first and second variable capacitances receives the control-signal for tuning the tunable resonant circuit. A timer-circuit generates a timing-signal based upon the input reference-signal and a reset-signal. A calibration-circuit controls which capacitances of the set of capacitances are connected between the first and second nodes, in response to the timing-signal and a comparison between a threshold and a voltage-signal that is based upon auxiliary pulsed currents generated based upon the first and second digital control signals.