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公开(公告)号：US11463720B2
公开(公告)日：2022-10-04
申请号：US16142497
申请日：2018-09-26
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Marinelli , Riccardo Gemelli
IPC: H04N19/467 , H04N19/176 , H04N19/87 , H04N19/172 , G06F21/60 , H04N19/426 , H04N19/68
Abstract: A method, includes: storing at least one set of data in a memory space, wherein the at least one set of data stored has a memory footprint in the memory space; and coupling, to the at least one set of data, a respective counter indicative of the at least one set of data, wherein the respective counter is embedded in the at least one set of data without increasing the memory footprint in the memory space.
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公开(公告)号：US10528422B2
公开(公告)日：2020-01-07
申请号：US15810731
申请日：2017-11-13
Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS
Inventor： Om Ranjan , Riccardo Gemelli , Denis Dutey
Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
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公开(公告)号：US20190146868A1
公开(公告)日：2019-05-16
申请号：US15810731
申请日：2017-11-13
Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS
Inventor： Om Ranjan , Riccardo Gemelli , Denis Dutey
Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
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公开(公告)号：US11436162B2
公开(公告)日：2022-09-06
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
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公开(公告)号：US20200379924A1
公开(公告)日：2020-12-03
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
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Patent Agency Ranking
公开(公告)号：US10379937B2
公开(公告)日：2019-08-13
申请号：US15798916
申请日：2017-10-31
Inventor： Om Ranjan , Riccardo Gemelli , Abhishek Gupta
Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
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公开(公告)号：US11055173B2
公开(公告)日：2021-07-06
申请号：US16703672
申请日：2019-12-04
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Om Ranjan , Riccardo Gemelli , Denis Dutey
Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
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公开(公告)号：US10860415B2
公开(公告)日：2020-12-08
申请号：US16454365
申请日：2019-06-27
Inventor： Om Ranjan , Riccardo Gemelli , Abhishek Gupta
Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
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公开(公告)号：US20190098327A1
公开(公告)日：2019-03-28
申请号：US16142497
申请日：2018-09-26
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Marinelli , Riccardo Gemelli
IPC: H04N19/467 , H04N19/176 , G06F21/60 , H04N19/172 , H04N19/87
Abstract: A method, includes: storing at least one set of data in a memory space, wherein the at least one set of data stored has a memory footprint in the memory space; and coupling, to the at least one set of data, a respective counter indicative of the at least one set of data, wherein the respective counter is embedded in the at least one set of data without increasing the memory footprint in the memory space.
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公开(公告)号：US20190129790A1
公开(公告)日：2019-05-02
申请号：US15798916
申请日：2017-10-31
Inventor： Om Ranjan , Riccardo Gemelli , Abhishek Gupta
CPC classification number: G06F11/10 , G06F3/0619 , G06F3/064 , G06F3/0673 , H04L1/0045 , H04L1/0063 , H04L1/0082
Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
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