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公开(公告)号：US10651641B2
公开(公告)日：2020-05-12
申请号：US15637766
申请日：2017-06-29
Inventor： Mauro Giacomini , Rajesh Narwal , Pravesh Kumar Saini
Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.
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公开(公告)号：US20180175606A1
公开(公告)日：2018-06-21
申请号：US15637766
申请日：2017-06-29
Inventor： Mauro Giacomini , Rajesh Narwal , Pravesh Kumar Saini
CPC classification number: H02H3/087 , H01L27/0248 , H02H3/04 , H02H3/20 , H02H7/20 , H02H9/042 , H02H9/046 , H02J9/061
Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.
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公开(公告)号：US09753480B2
公开(公告)日：2017-09-05
申请号：US13962958
申请日：2013-08-09
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal
CPC classification number: G05F3/08 , G05F1/46 , G05F1/462 , G05F1/468 , G05F1/56 , G05F1/565 , H02M2001/0025
Abstract: An embodiment of an arrangement includes a voltage regulator configured to provide an output voltage, said voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, said selection signal being used to control which of said regulator reference voltages said voltage regulator receives.
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公开(公告)号：US20240402738A1
公开(公告)日：2024-12-05
申请号：US18326876
申请日：2023-05-31
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Shashwat
Abstract: The present disclosure is directed to a fully analog voltage regulator circuit with reference modulation. The voltage regulator circuit includes a low-dropout regulator, a voltage-to-current convert, a resistor-capacitor filter circuit, and an operational amplifier voltage buffer. The voltage regulator circuit minimizes dropout voltage of the circuit by comparing the output voltage of the voltage regulator to a reference voltage and adjusting the output voltage of the op amp voltage buffer, accordingly. The voltage regulator circuit includes two operational amplifiers, wherein the negative input of a first of the two operational amplifiers is coupled to the negative input of a second of the two operational amplifiers through the resistor-capacitor filter circuit.
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公开(公告)号：US10680587B2
公开(公告)日：2020-06-09
申请号：US16027762
申请日：2018-07-05
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Pravesh Kumar Saini
IPC: H03K3/0231 , H03K4/502 , H03K5/19 , H03K3/011
Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.
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Patent Agency Ranking
公开(公告)号：US20170351289A1
公开(公告)日：2017-12-07
申请号：US15685763
申请日：2017-08-24
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal
CPC classification number: G05F3/08 , G05F1/46 , G05F1/462 , G05F1/468 , G05F1/56 , G05F1/565 , H02M2001/0025
Abstract: A voltage regulator provides an output voltage, the voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, the selection signal being used to control which of the regulator reference voltages the voltage regulator receives.
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公开(公告)号：US12203982B2
公开(公告)日：2025-01-21
申请号：US17663561
申请日：2022-05-16
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/30 , G01R31/317 , G01R31/3173 , G01R31/319
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.
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公开(公告)号：US11726514B2
公开(公告)日：2023-08-15
申请号：US17242067
申请日：2021-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Shashwat , Rajesh Narwal
Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.
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公开(公告)号：US09971372B2
公开(公告)日：2018-05-15
申请号：US15685763
申请日：2017-08-24
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal
CPC classification number: G05F3/08 , G05F1/46 , G05F1/462 , G05F1/468 , G05F1/56 , G05F1/565 , H02M2001/0025
Abstract: A voltage regulator provides an output voltage, the voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, the selection signal being used to control which of the regulator reference voltages the voltage regulator receives.
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公开(公告)号：US20220276302A1
公开(公告)日：2022-09-01
申请号：US17663561
申请日：2022-05-16
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/30 , G01R31/3173 , G01R31/319 , G01R31/317
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.
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