公开(公告)号：US20170133390A1

公开(公告)日：2017-05-11

申请号：US15413497

申请日：2017-01-24

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

公开(公告)号：US09589968B2

公开(公告)日：2017-03-07

申请号：US14952662

申请日：2015-11-25

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

Abstract translation: 集成电路包括具有位于掩埋绝缘层上方的半导体膜的绝缘体上硅衬底。 一次可编程类型的至少一个存储单元包括具有第一电极区域的MOS电容器，该第一电极区域包括至少部分硅化并且侧壁为绝缘横向区域的栅极区域，位于栅极区域和半导体膜之间的电介质层 以及包括半导体膜的硅化物区域的第二电极区域，位于绝缘横向区域旁边并且至少部分地延伸到介电层下方。

公开(公告)号：US09881928B2

公开(公告)日：2018-01-30

申请号：US15413497

申请日：2017-01-24

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

公开(公告)号：US20160343720A1

公开(公告)日：2016-11-24

申请号：US14952662

申请日：2015-11-25

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

Abstract translation: 集成电路包括具有位于掩埋绝缘层上方的半导体膜的绝缘体上硅衬底。 一次可编程类型的至少一个存储单元包括具有第一电极区域的MOS电容器，该第一电极区域包括至少部分硅化并且侧壁为绝缘横向区域的栅极区域，位于栅极区域和半导体膜之间的电介质层 以及包括半导体膜的硅化物区域的第二电极区域，位于绝缘横向区域旁边并且至少部分地延伸到介电层下方。