公开(公告)号：US20150116029A1

公开(公告)日：2015-04-30

申请号：US14523996

申请日：2014-10-27

Applicant: STMicroelectronics SA

Inventor： Antoine Litty ,  Sylvie Ortolland

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/1087 ,  H01L29/78624 ,  H01L29/78648 ,  H03K17/687

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract translation: 延伸漏极晶体管形成在绝缘层的一侧上的半导体层中，半导体区域布置在绝缘层的另一侧上。 半导体区域包括布置在源极的前面的第一导电类型的第一部分和栅极的至少一个较大部分和布置在延伸漏极区域的至少较大部分的前面的第二导电类型的第二部分 所述第一和第二部分中的每一个耦合到连接垫。

公开(公告)号：US09373714B2

公开(公告)日：2016-06-21

申请号：US14523996

申请日：2014-10-27

Applicant: STMicroelectronics SA

Inventor： Antoine Litty ,  Sylvie Ortolland

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H03K17/687

CPC classification number: H01L29/7824 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/1087 ,  H01L29/78624 ,  H01L29/78648 ,  H03K17/687

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract translation: 延伸漏极晶体管形成在绝缘层的一侧上的半导体层中，半导体区域布置在绝缘层的另一侧上。 半导体区域包括布置在源极的前面的第一导电类型的第一部分和栅极的至少一个较大部分和布置在延伸漏极区域的至少较大部分的前面的第二导电类型的第二部分 所述第一和第二部分中的每一个耦合到连接垫。