公开(公告)号：US20180323196A1

公开(公告)日：2018-11-08

申请号：US16038705

申请日：2018-07-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Florian Cacho ,  Vincent Huard

IPC: H01L27/092 ,  H03K19/21 ,  H03K19/094 ,  H03K19/003 ,  G01R31/317 ,  H01L29/10 ,  H03K3/037 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  G01R31/31725 ,  H01L21/823892 ,  H01L29/1083 ,  H03K3/037 ,  H03K19/00315 ,  H03K19/094 ,  H03K19/21

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.

公开(公告)号：US10585143B2

公开(公告)日：2020-03-10

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal Urard ,  Florian Cacho ,  Vincent Huard ,  Alok Kumar Tripathi

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181 ,  G06F17/50

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

公开(公告)号：US20180130803A1

公开(公告)日：2018-05-10

申请号：US15609571

申请日：2017-05-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Florian Cacho ,  Vincent Huard

IPC: H01L27/092 ,  H03K3/037 ,  H03K19/21 ,  H01L29/10

CPC classification number: H01L27/0928 ,  G01R31/31725 ,  H01L21/823892 ,  H01L29/1083 ,  H03K3/037 ,  H03K19/00315 ,  H03K19/094 ,  H03K19/21

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.

公开(公告)号：US20150142410A1

公开(公告)日：2015-05-21

申请号：US14541627

申请日：2014-11-14

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Salim Ighilahriz ,  Florian Cacho ,  Vincent Huard

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

Abstract: A method of circuit simulation includes: simulating, by a processing device, behavior of a heterojunction bipolar transistor device based on at least a first base-emitter voltage of the transistor to determine a first base or collector current density of the HBT device; and determining whether the application of the first base-emitter voltage to the HBT device will result in base current degradation by performing a first comparison of the first current density with a first current density limit.

Abstract translation: 一种电路仿真的方法包括：通过处理器件模拟基于晶体管的至少第一基极 - 发射极电压的异质结双极晶体管器件的行为，以确定HBT器件的第一基极或集电极电流密度; 以及通过执行所述第一电流密度与第一电流密度极限的第一比较来确定是否将所述第一基极 - 发射极电压施加到所述HBT器件将导致基极电流劣化。

公开(公告)号：US10050037B2

公开(公告)日：2018-08-14

申请号：US15609571

申请日：2017-05-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Florian Cacho ,  Vincent Huard

IPC: H03K3/01 ,  H01L27/092 ,  H03K3/037 ,  H03K19/21 ,  H01L29/10

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.