公开(公告)号：US20230187413A1

公开(公告)日：2023-06-15

申请号：US18059974

申请日：2022-11-29

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Masahiro Yoshihara ,  Tz-Yi Liu ,  Raul Adrian Cernea ,  Shay Fux ,  Sagie Goldenberg ,  Eli Harari

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/06541

Abstract: In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.

公开(公告)号：US20230195314A1

公开(公告)日：2023-06-22

申请号：US18059971

申请日：2022-11-29

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Masahiro Yoshihara ,  Tz-Yi Liu ,  Raul Adrian Cernea ,  Shay Fux ,  Erez Landau ,  Sagie Goldenberg

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.