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    MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT WITH LARGE NUMBER OF INDEPENDENTLY ACCESSIBLE MEMORY BANKS
    1.
    发明公开
    MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT WITH LARGE NUMBER OF INDEPENDENTLY ACCESSIBLE MEMORY BANKS 审中-公开

    公开(公告)号：US20240045615A1

    公开(公告)日：2024-02-08

    申请号：US18357948

    申请日：2023-07-24

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Shay Fux ,  Sagie Goldenberg ,  Amotz Yagev

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0656 ,  G06F3/0659 ,  G06F3/0611 ,  G06F3/0679

    摘要： A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.

    MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT USING VIRTUAL BANK ADDRESSING
    2.
    发明公开
    MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT USING VIRTUAL BANK ADDRESSING 审中-公开

    公开(公告)号：US20240045594A1

    公开(公告)日：2024-02-08

    申请号：US18357952

    申请日：2023-07-24

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Shay Fux ,  Sagie Goldenberg ,  Shahar Sandor

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0656 ,  G06F3/0673

    摘要： A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.

    Memory Device Including Arrangement of Independently And Concurrently Operable Tiles of Memory Transistors
    3.
    发明公开
    Memory Device Including Arrangement of Independently And Concurrently Operable Tiles of Memory Transistors 审中-公开

    公开(公告)号：US20230187413A1

    公开(公告)日：2023-06-15

    申请号：US18059974

    申请日：2022-11-29

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Masahiro Yoshihara ,  Tz-Yi Liu ,  Raul Adrian Cernea ,  Shay Fux ,  Sagie Goldenberg ,  Eli Harari

    IPC分类号： H01L25/065 ,  H01L25/18

    CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L2225/06541

    摘要： In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.

    Memory System Implementing Write Abort Operation For Reduced Read Latency
    5.
    发明公开
    Memory System Implementing Write Abort Operation For Reduced Read Latency 审中-公开

    公开(公告)号：US20230195314A1

    公开(公告)日：2023-06-22

    申请号：US18059971

    申请日：2022-11-29

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Masahiro Yoshihara ,  Tz-Yi Liu ,  Raul Adrian Cernea ,  Shay Fux ,  Erez Landau ,  Sagie Goldenberg

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

    摘要： A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.