公开(公告)号：US20050231671A1

公开(公告)日：2005-10-20

申请号：US10488048

申请日：2002-06-21

申请人： Sahng-Ik Jun ,  Woon-Yong Park

发明人： Sahng-Ik Jun ,  Woon-Yong Park

IPC分类号： G02F1/1337 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/139 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/133707 ,  G02F1/1393

摘要： A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line.

摘要翻译： 在由数据线和栅极线限定的各个像素区域上形成有具有多个第一切口的第一绝缘基板上彼此相交的多条栅极线和多条数据线。 薄膜晶体管连接到每个像素电极。 具有多个第二切口的参考电极形成在与第一基板相对的第二基板上。 相对于一个数据线相对的相邻两个像素区域中的第一切口和第二切口具有相对于数据线的反转对称。

公开(公告)号：US06842213B2

公开(公告)日：2005-01-11

申请号：US10811049

申请日：2004-03-26

申请人： Il-Gon Kim ,  Woon-Yong Park ,  Byoung-Sun Na ,  Yu-Ri Song ,  Seung-Soo Baek ,  Young-Mi Tak ,  Sahng-Ik Jun

发明人： Il-Gon Kim ,  Woon-Yong Park ,  Byoung-Sun Na ,  Yu-Ri Song ,  Seung-Soo Baek ,  Young-Mi Tak ,  Sahng-Ik Jun

IPC分类号： G02F1/1337 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  G09F9/35 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/136213 ,  G02F1/133707 ,  G02F1/134336 ,  G02F2201/121

摘要： An LCD has a storage electrode wire between long sides of partitions of a pixel electrode and gate lines or data lines. A gate wire and a storage electrode wire are formed on a substrate and covered with a gate insulating layer. A data wire is formed on the gate insulating layer and covered with a passivation layer. A thin film transistor including gate, source and drain electrodes are provided on the substrate. A pixel electrode is formed on the passivation layer and connected to the drain electrode. The pixel electrode is divided into three partitions, a first one having long and short sides parallel to data lines and gate lines, respectively, and second and third ones vice versa. A storage electrode line and some storage electrodes are disposed between the long sides of the partitions and the gate or the data lines, and between the long sides of the partitions. Other storage electrodes disposed between the short sides of the partitions and the gate or the data lines are covered by the pixel electrode. A storage electrode between the short side of the first portion and the long side of the partition is spaced apart from the first partition by at least 3 μm.

摘要翻译： LCD在像素电极的隔板的长边和栅极线或数据线之间具有存储电极线。 栅极线和存储电极线形成在基板上并被栅极绝缘层覆盖。 数据线形成在栅极绝缘层上并被钝化层覆盖。 在基板上设置包括栅极，源极和漏极的薄膜晶体管。 像素电极形成在钝化层上并连接到漏电极。 像素电极被分成三个分区，第一分隔板分别具有与数据线和栅极线平行的长边和短边，第二和第三分隔物反之亦然。 存储电极线和一些存储电极设置在隔板的长边和栅极或数据线之间以及隔板的长边之间。 设置在隔板的短边和栅极或数据线之间的其他存储电极被像素电极覆盖。 第一部分的短边与隔板的长边之间的存储电极与第一隔板间隔至少3毫米。

公开(公告)号：US06555876B2

公开(公告)日：2003-04-29

申请号：US10073459

申请日：2002-02-11

申请人： Sahng-Ik Jun ,  Yu-Ri Song ,  Woon-Yong Park

发明人： Sahng-Ik Jun ,  Yu-Ri Song ,  Woon-Yong Park

IPC分类号： H01L2701

CPC分类号： G02F1/136259 ,  G02F2001/136263 ,  H01L21/76894 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film transistor array substrate includes an insulating substrate, and gate lines formed on the substrate, storage electrode lines and storage electrodes are also formed on the substrate. Data lines cross over the gate lines and the storage electrode lines. The data lines are electrically insulated from the gate lines and the storage electrode lines. Thin film transistors are connected to the data lines and the gate lines, and pixel electrodes are connected to the thin film transistors. Bridges are formed at the same plane as the pixel electrodes while interconnecting the storage electrode lines and the storage electrodes placed at both sides of the gate lines. The storage electrode lines and the storage electrodes have protrusions or grooves placed close to the bridges to indicate the locations of laser illumination.

摘要翻译： 薄膜晶体管阵列基板包括绝缘基板，形成在基板上的栅极线，存储电极线和存储电极也形成在基板上。 数据线跨越栅极线和存储电极线。 数据线与栅极线和存储电极线电绝缘。 薄膜晶体管连接到数据线和栅极线，并且像素电极连接到薄膜晶体管。 在与存储电极线和设置在栅极线的两侧的存储电极互连的同时，将桥与像素电极形成在同一平面上。 存储电极线和存储电极具有靠近桥的放置或凹槽，以指示激光照明的位置。

公开(公告)号：US06771343B2

公开(公告)日：2004-08-03

申请号：US10054079

申请日：2002-01-22

申请人： Il-Gon Kim ,  Woon-Yong Park ,  Byoung-Sun Na ,  Yu-Ri Song ,  Seung-Soo Baek ,  Young-Mi Tak ,  Sahng-Ik Jun

发明人： Il-Gon Kim ,  Woon-Yong Park ,  Byoung-Sun Na ,  Yu-Ri Song ,  Seung-Soo Baek ,  Young-Mi Tak ,  Sahng-Ik Jun

IPC分类号： G02F11343

CPC分类号： G02F1/136213 ,  G02F1/133707 ,  G02F1/134336 ,  G02F2201/121

摘要： An LCD has a storage electrode wire between long sides of partitions of a pixel electrode and gate lines or data lines. A gate wire and a storage electrode wire are formed on a substrate and covered with a gate insulating layer. A data wire is formed on the gate insulating layer and covered with a passivation layer. A thin film transistor including gate, source and drain electrodes are provided on the substrate. A pixel electrode is formed on the passivation layer and connected to the drain electrode. The pixel electrode is divided into three partitions, a first one having long and short sides parallel to data lines and gate lines, respectively, and second and third ones vice versa. A storage electrode line and some storage electrodes are disposed between the long sides of the partitions and the gate or the data lines, and between the long sides of the partitions. Other storage electrodes disposed between the short sides of the partitions and the gate or the data lines are covered by the pixel electrode. A storage electrode between the short side of the first portion and the long side of the partition is spaced apart from the first partition by at least 3 &mgr;m.

摘要翻译： LCD在像素电极的隔板的长边和栅极线或数据线之间具有存储电极线。 栅极线和存储电极线形成在基板上并被栅极绝缘层覆盖。 数据线形成在栅极绝缘层上并被钝化层覆盖。 在基板上设置包括栅极，源极和漏极的薄膜晶体管。 像素电极形成在钝化层上并连接到漏电极。 像素电极被分成三个分区，第一分隔板分别具有与数据线和栅极线平行的长边和短边，第二和第三分隔物反之亦然。 存储电极线和一些存储电极设置在隔板的长边和栅极或数据线之间以及隔板的长边之间。 设置在隔板的短边和栅极或数据线之间的其他存储电极被像素电极覆盖。 第一部分的短边与隔板的长边之间的存储电极与第一隔板间隔至少3毫米。

公开(公告)号：US07709304B2

公开(公告)日：2010-05-04

申请号：US11824879

申请日：2007-07-02

申请人： Woon-Yong Park ,  Won-Hee Lee ,  Il-Gon Kim ,  Seung-Taek Lim ,  You-Lee Song ,  Sahng-Ik Jun

发明人： Woon-Yong Park ,  Won-Hee Lee ,  Il-Gon Kim ,  Seung-Taek Lim ,  You-Lee Song ,  Sahng-Ik Jun

IPC分类号： H01L21/00

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  G03F1/00

摘要： A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

摘要翻译： 沉积钝化层并形成光致抗蚀剂。 光致抗蚀剂包括具有减小的厚度的第一至第三部分，第二部分位于漏电极和数据线的部分上，第三部分位于栅极线的部分上。 用于形成光致抗蚀剂的掩模具有在对应于第二部分的区域上具有约0.8-2.0微米的宽度和距离的直线狭缝。 蚀刻钝化层和底层半导体层以及光致抗蚀剂以暴露在光致抗蚀剂的第三部分之下的栅绝缘层的部分以及在光致抗蚀剂的第二部分下的钝化层的部分。 去除钝化层和栅极绝缘层的暴露部分，以暴露出漏电极，栅极线和数据线以及随后被去除的部分半导体层。

公开(公告)号：US20090111204A1

公开(公告)日：2009-04-30

申请号：US12340479

申请日：2008-12-19

申请人： Sahng-Ik JUN ,  Woon-Yong Park

发明人： Sahng-Ik JUN ,  Woon-Yong Park

IPC分类号： H01L21/02

CPC分类号： G02F1/133707 ,  G02F1/1393

摘要： A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line.

摘要翻译： 在由数据线和栅极线限定的各个像素区域上形成有具有多个第一切口的第一绝缘基板上彼此相交的多条栅极线和多条数据线。 薄膜晶体管连接到每个像素电极。 具有多个第二切口的参考电极形成在与第一基板相对的第二基板上。 相对于一个数据线相对的相邻两个像素区域中的第一切口和第二切口具有相对于数据线的反转对称。

公开(公告)号：US07483105B2

公开(公告)日：2009-01-27

申请号：US10488048

申请日：2002-06-21

申请人： Sahng-Ik Jun ,  Woon-Yong Park

发明人： Sahng-Ik Jun ,  Woon-Yong Park

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707 ,  G02F1/1393

摘要： A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line.

摘要翻译： 在由数据线和栅极线限定的各个像素区域上形成有具有多个第一切口的第一绝缘基板上彼此相交的多条栅极线和多条数据线。 薄膜晶体管连接到每个像素电极。 具有多个第二切口的参考电极形成在与第一基板相对的第二基板上。 相对于一个数据线相对的相邻两个像素区域中的第一切口和第二切口具有相对于数据线的反转对称。

公开(公告)号：US20070259289A1

公开(公告)日：2007-11-08

申请号：US11824879

申请日：2007-07-02

申请人： Woon-Yong Park ,  Won-Hee Lee ,  Il-Gon Kim ,  Seung-Taek Lim ,  You-Lee Song ,  Sahng-Ik Jun

发明人： Woon-Yong Park ,  Won-Hee Lee ,  Il-Gon Kim ,  Seung-Taek Lim ,  You-Lee Song ,  Sahng-Ik Jun

IPC分类号： G03C5/00

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  G03F1/00

摘要： A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

摘要翻译： 沉积钝化层并形成光致抗蚀剂。 光致抗蚀剂包括具有减小的厚度的第一至第三部分，第二部分位于漏电极和数据线的部分上，第三部分位于栅极线的部分上。 用于形成光致抗蚀剂的掩模具有在对应于第二部分的区域上具有约0.8-2.0微米的宽度和距离的直线狭缝。 蚀刻钝化层和底层半导体层以及光致抗蚀剂以暴露在光致抗蚀剂的第三部分之下的栅极绝缘层的部分以及在光致抗蚀剂的第二部分下的钝化层的部分。 去除钝化层和栅极绝缘层的暴露部分，以露出漏电极，栅极线和数据线以及随后被去除的部分半导体层。

公开(公告)号：US06816220B2

公开(公告)日：2004-11-09

申请号：US10108774

申请日：2002-03-28

申请人： Seung-Soo Baek ,  Woon-Yong Park ,  Sahng-IK Jun ,  Il-Gon Kim ,  Byoung-Sun Na ,  Young-Mi Tak ,  Yu-Ri Song

发明人： Seung-Soo Baek ,  Woon-Yong Park ,  Sahng-IK Jun ,  Il-Gon Kim ,  Byoung-Sun Na ,  Young-Mi Tak ,  Yu-Ri Song

IPC分类号： G02F11343

CPC分类号： G02F1/134336 ,  G02F1/133707 ,  G02F2001/134318 ,  G02F2201/121

摘要： A liquid crystal display includes: a first substrate; a first signal line formed on the first substrate and extending in a direction; a second signal line intersecting the first signal line while being insulated; a pixel electrode formed in a pixel area defined by intersections of the first signal line and the second signal line, the pixel electrode having a plurality of partitions; a switching element connected to the first signal line, the second signal line, and the pixel electrode; a second substrate opposite the first substrate; a black matrix formed on the second substrate; and a common electrode formed over the second substrate having a plurality of domain defining members, wherein each domain is enclosed by the partitions of the pixel electrode and the domain defining members and has at least one long side parallel or perpendicular to the first signal line and at least one short side curved at an angle of about 30 to about 60 degrees with the first signal line.

公开(公告)号：USRE43575E1

公开(公告)日：2012-08-14

申请号：US10218968

申请日：2002-08-14

申请人： Byoung-Sun Na ,  Dong-Gyu Kim ,  Woon-Yong Park

发明人： Byoung-Sun Na ,  Dong-Gyu Kim ,  Woon-Yong Park

IPC分类号： G02F1/1345

CPC分类号： G02F1/1345

摘要： A liquid crystal display (LCD) panel includes a substrate, a plurality of parallel control lines on the substrate, and a bonding pad area on the substrate having a plurality of bonding pads therein. A respective one of a plurality of interconnecting conductors connect a respective bonding pad of the bonding pad area to a respective one of the plurality of parallel control lines, each of the plurality of interconnecting conductors having a uniform resistance. According to embodiments of the invention, an interconnecting conductor of the plurality of interconnecting conductors may include a material selected to provide the uniform resistance. The interconnecting conductor may include a first portion including a first material having a first resistivity and a second portion including a second material having a second resistivity different from the first resistivity. The first and second portions may have respective first and second lengths selected to provide the uniform resistance. According to other embodiments, an interconnecting conductor of the plurality of interconnecting conductors may have a width selected to provide the uniform resistance. In one embodiment, the plurality of interconnecting conductors have a resistivity per unit length associated therewith and extend from the bonding pad area in a fanned configuration, with the resistivity of the interconnecting conductors increasing toward a medial portion of the fanned configuration. The width of the interconnecting conductors may decrease towards the medial portion of the fanned configuration to produce the desired resistivity. According to other embodiments, an interconnecting conductor of the plurality of interconnecting conductors has a length selected to provide the uniform resistance. In one embodiment, the interconnecting conductor has a serpentine portion to provide the desired length.

摘要翻译： 液晶显示器（LCD）面板包括衬底，在衬底上的多个并行控制线，以及衬底上的焊盘区域，其中具有多个焊盘。 多个互连导体中的相应一个将接合焊盘区域的相应接合焊盘连接到多个并联控制线中的相应一个，多个互连导体中的每一个具有均匀的电阻。 根据本发明的实施例，多个互连导体的互连导体可以包括被选择以提供均匀电阻的材料。 互连导体可以包括包括具有第一电阻率的第一材料的第一部分和包括具有不同于第一电阻率的第二电阻率的第二材料的第二部分。 第一和第二部分可以具有相应的第一和第二长度，以提供均匀的电阻。 根据其他实施例，多个互连导体的互连导体可以具有被选择为提供均匀电阻的宽度。 在一个实施例中，多个互连导体具有与其相关联的每单位长度的电阻率，并且从结合焊盘区域以扇形配置延伸，互连导体的电阻率朝着扇形结构的中间部分增加。 互连导体的宽度可以朝着扇形构型的中间部分减小以产生所需的电阻率。 根据其他实施例，多个互连导体的互连导体具有选择的长度以提供均匀的电阻。 在一个实施例中，互连导体具有蛇形部分以提供期望的长度。