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    Address Remapping Using Interconnect Routing Identification Bits
    1.
    发明申请
    Address Remapping Using Interconnect Routing Identification Bits 审中-公开
    使用互连路由识别位的地址重映射

    公开(公告)号：US20140006644A1

    公开(公告)日：2014-01-02

    申请号：US13536647

    申请日：2012-06-28

    申请人： Sakthivel Komarasamy Pullagoundapatti ,  Krishna Venkanna Bhandi ,  Chithambaranathan G ,  Claus Pribbernow ,  Shrinivas Sureban

    发明人： Sakthivel Komarasamy Pullagoundapatti ,  Krishna Venkanna Bhandi ,  Chithambaranathan G ,  Claus Pribbernow ,  Shrinivas Sureban

    IPC分类号： G06F3/00

    CPC分类号： G06F12/0284 ,  Y02D10/13

    摘要： A method for mapping addresses between one or more master devices and at least one common slave device in a multiprocessor system is provided, the system including a bus interconnect for interfacing between the master devices and the common slave device. The method includes steps of: receiving a first address corresponding to a bus transaction between a given one of the one or more master devices and the common slave device; decoding a unique identifier associated with the given one of the one or more master devices; and generating a second address as a function of the first address and the unique identifier for remapping access to the common slave device by the given one of the one or more master devices.

    摘要翻译： 提供了一种用于在多处理器系统中映射一个或多个主设备与至少一个公共从设备之间的地址的方法，该系统包括用于在主设备和公共从设备之间进行接口的总线互连。 该方法包括以下步骤：接收对应于所述一个或多个主设备中的给定一个与所述公共从设备之间的总线事务的第一地址; 解码与所述一个或多个主设备中的给定一个相关联的唯一标识符; 以及生成作为所述第一地址的函数的第二地址和所述唯一标识符，用于由所述一个或多个主设备中的给定一个重新映射对所述公共从设备的访问。

    METHODS AND APPARATUS FOR INCREASING DEVICE ACCESS PERFORMANCE IN DATA PROCESSING SYSTEMS
    2.
    发明申请
    METHODS AND APPARATUS FOR INCREASING DEVICE ACCESS PERFORMANCE IN DATA PROCESSING SYSTEMS 审中-公开
    数据处理系统中增加设备访问性能的方法和设备

    公开(公告)号：US20130111181A1

    公开(公告)日：2013-05-02

    申请号：US13286109

    申请日：2011-10-31

    申请人： Srinivasa Rao Kothamasu ,  George Wayne Nation ,  Krishna Venkanna Bhandi

    发明人： Srinivasa Rao Kothamasu ,  George Wayne Nation ,  Krishna Venkanna Bhandi

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0284 ,  G06F12/06 ,  G06F12/0888 ,  G06F2212/1008 ,  G06F2212/206

    摘要： A data processing system comprises a device and device access circuitry. The device is mapped to a first mapped address region and to a second mapped address region. The device access circuitry, in turn, is operative to access the device in accordance with a first set of memory attributes when addressing the device within the first mapped address region and to access the device in accordance with a second set of memory attributes when addressing the device within the second mapped address region. The first set of memory attributes is different from the second set of memory attributes.

    摘要翻译： 数据处理系统包括设备和设备访问电路。 该设备被映射到第一映射地址区域和第二映射地址区域。 在寻址第一映射地址区域内的设备时，设备访问电路又可操作以根据第一组存储器属性访问设备，并且当寻址存储器属性时，根据第二组存储器属性访问设备 设备在第二映射地址区域内。 第一组内存属性与第二组内存属性不同。