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1.发明申请METHODS AND APPARATUS FOR INCREASING DEVICE ACCESS PERFORMANCE IN DATA PROCESSING SYSTEMS 审中-公开数据处理系统中增加设备访问性能的方法和设备公开(公告)号：US20130111181A1
公开(公告)日：2013-05-02
申请号：US13286109
申请日：2011-10-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0284 , G06F12/06 , G06F12/0888 , G06F2212/1008 , G06F2212/206
摘要： A data processing system comprises a device and device access circuitry. The device is mapped to a first mapped address region and to a second mapped address region. The device access circuitry, in turn, is operative to access the device in accordance with a first set of memory attributes when addressing the device within the first mapped address region and to access the device in accordance with a second set of memory attributes when addressing the device within the second mapped address region. The first set of memory attributes is different from the second set of memory attributes.
摘要翻译： 数据处理系统包括设备和设备访问电路。 该设备被映射到第一映射地址区域和第二映射地址区域。 在寻址第一映射地址区域内的设备时，设备访问电路又可操作以根据第一组存储器属性访问设备，并且当寻址存储器属性时，根据第二组存储器属性访问设备 设备在第二映射地址区域内。 第一组内存属性与第二组内存属性不同。
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公开(公告)号：US08924779B2
公开(公告)日：2014-12-30
申请号：US13435613
申请日：2012-03-30
IPC分类号： G06F11/00
CPC分类号： G06F11/0757 , G06F11/079 , G06F11/1428
摘要： An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response information as a function of the status information relating to the slave device for detecting and/or responding to hardware system anomalies in a manner which reduces a need for resetting the hardware system to return to normal operation.
摘要翻译： 提供一种用于处理硬件系统中的异常的装置，包括主设备和通过互连设备与主设备耦合的至少一个从设备。 该装置包括至少一个控制器，用于接收与从属设备相关的状态信息。 状态信息表示从属设备和/或互连设备中是否存在异常。 控制器可操作以根据与从属设备有关的状态信息的函数产生输出响应信息，用于以减少硬件系统复位以恢复正常操作的方式检测和/或响应硬件系统异常。
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公开(公告)号：US20130262918A1
公开(公告)日：2013-10-03
申请号：US13435613
申请日：2012-03-30
IPC分类号： G06F11/267 , G06F11/16 , G06F11/00
CPC分类号： G06F11/0757 , G06F11/079 , G06F11/1428
摘要： An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response information as a function of the status information relating to the slave device for detecting and/or responding to hardware system anomalies in a manner which reduces a need for resetting the hardware system to return to normal operation.
摘要翻译： 提供一种用于处理硬件系统中的异常的装置，包括主设备和通过互连设备与主设备耦合的至少一个从设备。 该装置包括至少一个控制器，用于接收与从属设备相关的状态信息。 状态信息表示从属设备和/或互连设备中是否存在异常。 控制器可操作以根据与从属设备有关的状态信息的函数产生输出响应信息，用于以减少硬件系统复位以恢复正常操作的方式检测和/或响应硬件系统异常。
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4.发明授权Flexible template having embedded gate array and composable memory for integrated circuits 有权具有嵌入式门阵列和集成电路可组合存储器的灵活模板公开(公告)号：US07831653B2
公开(公告)日：2010-11-09
申请号：US10318792
申请日：2002-12-13
申请人： George Wayne Nation , Gary Scott Delp , William D. Scharf , Narayanan Raman , John N. Fryar, III , Majid Bemanian
发明人： George Wayne Nation , Gary Scott Delp , William D. Scharf , Narayanan Raman , John N. Fryar, III , Majid Bemanian
IPC分类号： G06F15/16
CPC分类号： H04L69/12
摘要： A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.
摘要翻译： 包括片和多个壳的部分制造的半导体芯片是用于通信和网络芯片的模板。 该片具有多个I / O端口，块和PHY。 硬件PHY被建立为对应于高速数据传输协议。 模板的内部包括逻辑门阵列和可配置存储器。 一旦选择了数据接收和传输的特定协议，逻辑门阵列和可配置存储器可以被编程，否则被配置为开发用于数据联网和通信的协议层。
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5.发明授权Composable system-in-package integrated circuits and process of composing the same 失效可组合的系统级封装集成电路及其组成过程公开(公告)号：US07491579B2
公开(公告)日：2009-02-17
申请号：US11079028
申请日：2005-03-14
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： H01L21/00
CPC分类号： G06F17/5045 , G06F2217/64
摘要： An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.
摘要翻译： 用于执行多个硬和软功能的SIP包括安装到基板的标准IC裸片和定制平台。 针对每个标准硬功能（例如存储器，处理，I / O和其他标准功能）识别芯片，并且选择一个或多个用户可配置的基本平台，当配置时，执行定制软件功能。 可选地，将基底层压到模具上，并将平台附接到基底。 通过定义耦合到表示芯片及其连接的逻辑的配置的基础平台并在组合上执行放置和时序闭合来执行测试。
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6.发明授权System and method for identifying valid portion of computer resource identifier 失效用于识别计算机资源标识符的有效部分的系统和方法
公开(公告)号：US6041324A
公开(公告)日：2000-03-21
申请号：US972106
申请日：1997-11-17
CPC分类号： H04L29/06 , G06F17/30887 , H04L29/12009 , H04L61/00 , H04L67/42 , Y10S707/99939 , Y10S707/99945
摘要： A system and method for receiving and validating user input for a computer resource entered into a computing system or network, and distinguishing valid and invalid portions of the user input. The invalid resource identifier, which ranges from a least specific portion to a most specific portion, is partitioned into a plurality of fields. At least one of the fields corresponding to the most specific portion of the invalid resource identifier is removed from the invalid resource identifier to create a modified resource identifier, wherein the modified resource identifier is used to attempt to access a higher level computer resource. The fields corresponding to the most specific portion of the resource identifier are removed until the modified resource identifier proves to be a valid resource identifier which can access a computer resource. The valid resource identifier is distinguished from the invalid resource identifier entered by the user, so that the user can easily determine a point at which the input is invalid.
摘要翻译： 一种用于接收和验证输入到计算系统或网络的计算机资源的用户输入以及区分用户输入的有效和无效部分的系统和方法。 从最小特定部分到最特定部分的无效资源标识符被划分为多个字段。 从无效资源标识符中删除与无效资源标识符的最具体部分相对应的字段中的至少一个，以创建修改的资源标识符，其中修改的资源标识符用于尝试访问较高级别的计算机资源。 删除对应于资源标识符的最具体部分的字段，直到修改的资源标识符被证明是可以访问计算机资源的有效资源标识符。 有效资源标识符与用户输入的无效资源标识不同，使用户可以容易地确定输入无效点。
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7.发明授权Indicating when clickable image link on a hypertext image map of a computer web browser has been traversed 失效指示计算机网络浏览器的超文本图像映射上的可点击图像链接已经遍历
公开(公告)号：US5983244A
公开(公告)日：1999-11-09
申请号：US721490
申请日：1996-09-27
申请人： George Wayne Nation
发明人： George Wayne Nation
CPC分类号： G06F17/30899
摘要： The invention is a method to mark hypertext links in an image map that have been traversed. The invention actually modifies the image map of the links by inserting a marker or changing the color associated with the coordinates of a particular image link on the image map. The history files of links that have been traversed are first checked to determine if the image has changed or is otherwise out of date. The image map or a copy of the image map is then modified and displayed.
摘要翻译： 本发明是用于标记已经遍历的图像映射中的超文本链接的方法。 本发明通过在图像映射上插入标记或改变与特定图像链接的坐标相关联的颜色来实际地修改链接的图像映射。 首先检查已经遍历的链接的历史文件，以确定图像是否已更改或过时。 然后修改和显示图像映射或图像映射的副本。
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公开(公告)号：US08484608B2
公开(公告)日：2013-07-09
申请号：US12576775
申请日：2009-10-09
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.
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9.发明申请公开(公告)号：US20090313416A1
公开(公告)日：2009-12-17
申请号：US12214030
申请日：2008-06-16
申请人： George Wayne Nation
发明人： George Wayne Nation
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , G06F12/0893 , G06F2212/202 , G06F2212/3042 , G06F2212/401 , G06F2212/7201 , G06F2212/7203 , G06F2212/7208
摘要： A main memory for a computer system comprises a controller including an interface to one or more processors, non-volatile memory, and volatile memory. The main memory comprises one or more contiguous range of real addresses supported by both the non-volatile memory and the volatile memory. The controller may be incorporated into a mainboard and the non-volatile memory and the volatile memory may comprise pluggable memory modules. Alternatively, the controller may be incorporated into a hybrid pluggable memory module including non-volatile memory and volatile memory. The controller may utilize the volatile memory as a cache for the non-volatile memory. One or more subsets of the non-volatile memory may be configured to contain a system image, an operating system managed emulated disk image, and/or an operating system managed a page-file. The controller may encrypt and/or compress data written to and/or decrypt and/or decompress data read from the non-volatile memory.
摘要翻译： 用于计算机系统的主存储器包括控制器，其包括到一个或多个处理器，非易失性存储器和易失性存储器的接口。 主存储器包括由非易失性存储器和易失性存储器支持的一个或多个连续的实际地址范围。 控制器可以并入主板，并且非易失性存储器和易失性存储器可以包括可插拔存储器模块。 或者，控制器可以并入包括非易失性存储器和易失性存储器的混合可插拔存储器模块中。 控制器可以利用易失性存储器作为非易失性存储器的缓存。 非易失性存储器的一个或多个子集可以被配置为包含系统映像，操作系统管理的仿真磁盘映像和/或管理页文件的操作系统。 控制器可以加密和/或压缩写入和/或解密和/或解压缩从非易失性存储器读取的数据的数据。
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10.发明授权Placement of configurable input/output buffer structures during design of integrated circuits 失效在集成电路设计期间配置输入/输出缓冲结构公开(公告)号：US06823502B2
公开(公告)日：2004-11-23
申请号：US10334568
申请日：2002-12-31
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.
摘要翻译： 考虑到产品的扩散可配置I / O块和/或I / O硬件的要求，用于设计集成电路和半导体产品的工具，为I / O缓冲结构生成正确的RTL。 给定部分制造的半导体产品的切片描述，设计者可以生成应用集的I / O资源。 然后给出具有晶体管结构以及扩散的可配置I / O块和/或I / O硬件以及多个伴随壳的应用组，这里的I / O生成工具自动读取具有切片描述的数据库和 从晶体管结构生成I / O缓冲结构。 I / O生成工具进一步调整并集成了具有自己的逻辑的客户的两个或两个客户的输入，并且请求特定的半导体产品或者从它们的预先建立的逻辑获得IP核。 I / O生成工具可以从晶体管结构创建正确的RTL，以正确布局，定时，测试和半导体产品的I / O缓冲放大器的功能，无论是增量还是全局。 一旦创建了I / O缓冲区结构，它们就被多个shell限定，包括验证shell，静态时序分析shell，制造测试shell和RTL分析shell。
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