公开(公告)号：US20240196594A1

公开(公告)日：2024-06-13

申请号：US18478978

申请日：2023-09-29

Applicant: Samsung Electronics Co .,LTD

Inventor： Hyeri AN ,  Dongsik Park ,  Sooho Shain ,  Joonsuk Park ,  Keonhee Park ,  Gaeun Lee ,  Jihoon Chang ,  Yujin Cho ,  Hana Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/01

Abstract: A semiconductor device includes a switching element, and a data storage structure electrically connected to the switching element. The data storage structure includes first electrodes, a second electrode, and a dielectric layer between the first electrodes and the second electrode. The second electrode includes a compound semiconductor layer doped with an impurity element, the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %.

公开(公告)号：US20240276707A1

公开(公告)日：2024-08-15

申请号：US18435680

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sinyeon Kim ,  Jooseong Yun ,  Jieun Lee ,  Hana Cho

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423

CPC classification number: H10B12/34 ,  H01L29/0649 ,  H01L29/4236

Abstract: A semiconductor device includes an active region, an isolation region on a side surface of the active region, a gate trench having a first trench portion crossing the active region and a second trench portion in the isolation region, a first gate portion within the first trench portion and a second gate portion within the second trench portion. The first gate portion and the second gate portion each includes a gate dielectric layer, a gate electrode on the gate dielectric layer, partially filling the gate trench, and having an upper surface disposed on a level lower than an upper end of the active region, and an insulative capping pattern on the gate electrode. The first gate portion includes a lower region, an intermediate region on the lower region, and an upper region on the intermediate region. A maximum width of the intermediate region is greater than a maximum width of the lower region and greater than a maximum width of the upper region.