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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240196594A1

    公开(公告)日：2024-06-13

    申请号：US18478978

    申请日：2023-09-29

    Applicant: Samsung Electronics Co .,LTD

    Inventor： Hyeri AN ,  Dongsik Park ,  Sooho Shain ,  Joonsuk Park ,  Keonhee Park ,  Gaeun Lee ,  Jihoon Chang ,  Yujin Cho ,  Hana Cho

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/01

    Abstract: A semiconductor device includes a switching element, and a data storage structure electrically connected to the switching element. The data storage structure includes first electrodes, a second electrode, and a dielectric layer between the first electrodes and the second electrode. The second electrode includes a compound semiconductor layer doped with an impurity element, the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230039205A1

    公开(公告)日：2023-02-09

    申请号：US17723747

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-sik Park ,  Joonsuk Park ,  Jihoon Chang

    IPC: H01L27/108

    Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230045674A1

    公开(公告)日：2023-02-09

    申请号：US17662306

    申请日：2022-05-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang

    IPC: H01L27/108

    Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

    CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    4.
    发明申请
    CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20240387608A1

    公开(公告)日：2024-11-21

    申请号：US18444322

    申请日：2024-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyooho Jung ,  Jongyeong Min ,  Jiye Baek ,  Joonsuk Park ,  Yeseul Lee ,  Jinwook Lee

    IPC: H01L27/08

    Abstract: A capacitor may include a primary lower electrode, an interface structure on a surface of the primary lower electrode, a primary dielectric layer including a metal oxide on the interface structure, the primary dielectric layer, and an upper electrode on the primary dielectric layer. The interface structure may include a first interface layer, a second interface layer, and a third interface layer. The first interface layer may have electrical conductivity, and may include a metal oxide doped with a pentavalent element. The second interface layer may be on the first interface layer, and may include a material further doped with nitrogen in the material of the first interface layer. The third interface layer may be on the second interface layer, and may include a metal oxide doped with nitrogen. A metal included in the metal oxide of the third interface layer may include a tetravalent metal.

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