Abstract:
A converter includes a feedback part, a pulse width modulation (PWM) controller and a PWM generator. The feedback part is configured to output a feedback signal based on a driving voltage. The PWM controller is configured to output a PWM control signal based on the feedback signal and a first compensation signal. The PWM generator is configured to control the driving voltage based on the PWM control signal. The first compensation signal is determined according to an occurrence of a predetermined pattern of an input image data.
Abstract:
A timing controller includes: a top voltage generator configured to output first to third top voltages; a bottom voltage generator configured to output first to third bottom voltages; a first transmitting part configured to output a first data signal for a first data driving chip, based on the first top and bottom voltages; a second transmitting part configured to output a second data signal for a second data driving chip based on the second top and bottom voltages; and a third transmitting part configured to output a third data signal for a third data driving chip based on the third top and bottom voltages, where one of the first to third top voltages is different from another of the first to third top voltages, and one of the first to third bottom voltages is different from another of the first to third bottom voltages.
Abstract:
A display device includes a display panel including a display area and a non-display area, a plurality of driver integrated circuits mounted on the non-display area of the display panel by a COG method, a printed circuit board (PCB) configured to provide a signal to the plurality of driver integrated circuits, and a flexible printed circuit (FPC) configured to transfer the signal from the PCB to the plurality of driver integrated circuits. The FPC has a first end portion and a second end portion opposite to the first end portion. The first end portion is attached on the non-display area of the display panel by a FOG method, and the second end portion is attached on the PCB. A width of the second end portion is different from a width of the first end portion.
Abstract:
A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.
Abstract:
A display substrate includes a pixel electrode disposed in a display area, a first pad part disposed in a first area of a peripheral area which is disposed adjacent to the display area, where the first pad part is electrically connected to a driver circuit, a second pad part disposed in a second area of the peripheral area facing the first pad part, where the second pad part is electrically connected to a flexible circuit film which transfers a transmission signal to the driver circuit, and a connection line part disposed in an area between the first and second pad parts as a vertical line type, where the connection line part connects the first and second pad parts to each other.