-
公开(公告)号：US09520099B2
公开(公告)日：2016-12-13
申请号：US14572682
申请日：2014-12-16
发明人： Bum Lee , Dong-In Kim , Yeon-Sun Na , Hyun-Seok Hong
CPC分类号： G09G3/3696 , G09G3/3611 , G09G2330/02 , H02M3/156 , H02M2001/0032 , H02M2001/0048 , Y02B70/1491 , Y02B70/16
摘要： A converter includes a feedback part, a pulse width modulation (PWM) controller and a PWM generator. The feedback part is configured to output a feedback signal based on a driving voltage. The PWM controller is configured to output a PWM control signal based on the feedback signal and a first compensation signal. The PWM generator is configured to control the driving voltage based on the PWM control signal. The first compensation signal is determined according to an occurrence of a predetermined pattern of an input image data.
摘要翻译： A转换器包括反馈部分，脉冲宽度调制（PWM）控制器和PWM发生器。 反馈部分被配置为基于驱动电压输出反馈信号。 PWM控制器被配置为基于反馈信号和第一补偿信号输出PWM控制信号。 PWM发生器被配置为基于PWM控制信号来控制驱动电压。 根据输入图像数据的预定图案的出现来确定第一补偿信号。
-
公开(公告)号：US09240159B2
公开(公告)日：2016-01-19
申请号：US14495132
申请日：2014-09-24
发明人： Yeon-Sun Na , Hyun-Seok Hong , Dong-In Kim , Ji-Hee Kim , Kwan-Young Oh , Bum Lee
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G3/3611 , G09G3/3696 , G09G5/18 , G09G2370/08
摘要： A timing controller includes: a top voltage generator configured to output first to third top voltages; a bottom voltage generator configured to output first to third bottom voltages; a first transmitting part configured to output a first data signal for a first data driving chip, based on the first top and bottom voltages; a second transmitting part configured to output a second data signal for a second data driving chip based on the second top and bottom voltages; and a third transmitting part configured to output a third data signal for a third data driving chip based on the third top and bottom voltages, where one of the first to third top voltages is different from another of the first to third top voltages, and one of the first to third bottom voltages is different from another of the first to third bottom voltages.
摘要翻译： 定时控制器包括：顶部电压发生器，被配置为输出第一至第三顶部电压; 底部电压发生器，被配置为输出第一至第三底部电压; 第一发送部件，被配置为基于所述第一顶部和底部电压输出用于第一数据驱动芯片的第一数据信号; 第二发送部件，被配置为基于所述第二顶部和底部电压输出用于第二数据驱动芯片的第二数据信号; 以及第三发送部，被配置为基于所述第三顶电压和所述第三至第三顶电压中的一个与所述第一至第三顶电压中的另一个不同的第三顶电压输出用于第三数据驱动芯片的第三数据信号，以及一 第一至第三底部电压与第一至第三底部电压中的另一个不同。
-
公开(公告)号：US20150230337A1
公开(公告)日：2015-08-13
申请号：US14527229
申请日：2014-10-29
发明人： DONG-IN KIM , Hyun-Seok Hong , Sang-Min Jeon , Joo-Yeon Won , Chong-Guk Lee
CPC分类号： H05K1/118 , H05K1/111 , H05K1/147 , H05K1/181 , H05K1/189 , H05K3/361 , H05K2201/10128 , Y10T29/49126
摘要： A display device includes a display panel including a display area and a non-display area, a plurality of driver integrated circuits mounted on the non-display area of the display panel by a COG method, a printed circuit board (PCB) configured to provide a signal to the plurality of driver integrated circuits, and a flexible printed circuit (FPC) configured to transfer the signal from the PCB to the plurality of driver integrated circuits. The FPC has a first end portion and a second end portion opposite to the first end portion. The first end portion is attached on the non-display area of the display panel by a FOG method, and the second end portion is attached on the PCB. A width of the second end portion is different from a width of the first end portion.
摘要翻译： 显示装置包括显示面板和非显示区域的显示面板，通过COG方法安装在显示面板的非显示区域上的多个驱动器集成电路，印刷电路板（PCB） 向多个驱动器集成电路提供的信号，以及被配置为将信号从PCB传送到多个驱动器集成电路的柔性印刷电路（FPC）。 FPC具有与第一端部相对的第一端部和第二端部。 第一端部通过FOG方法附着在显示面板的非显示区域上，第二端部附着在PCB上。 第二端部的宽度与第一端部的宽度不同。
-
公开(公告)号：US09984650B2
公开(公告)日：2018-05-29
申请号：US15141027
申请日：2016-04-28
发明人： Hyun-Seok Hong , Hyo-Chul Lee
CPC分类号： G09G5/003 , G09G3/2096 , G09G2300/0408 , G09G2300/0426 , G09G2310/0281 , G09G2310/08 , G09G2330/021 , G09G2330/06 , G09G2370/08 , H05K1/0228 , H05K1/0296 , H05K1/147 , H05K1/181 , H05K2201/058 , H05K2201/10128
摘要： A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.
-
公开(公告)号：US09412326B2
公开(公告)日：2016-08-09
申请号：US14510429
申请日：2014-10-09
发明人： Luck-Hyun Kim , Ji-Hyun Kwon , Sang-Moon Moh , Yeun-Mo Yeon , Hyun-Seok Hong
CPC分类号： G09G3/3688 , G09G2300/0426 , G09G2320/0223 , H01L27/124 , H01L27/15 , H01L33/36
摘要： A display substrate includes a pixel electrode disposed in a display area, a first pad part disposed in a first area of a peripheral area which is disposed adjacent to the display area, where the first pad part is electrically connected to a driver circuit, a second pad part disposed in a second area of the peripheral area facing the first pad part, where the second pad part is electrically connected to a flexible circuit film which transfers a transmission signal to the driver circuit, and a connection line part disposed in an area between the first and second pad parts as a vertical line type, where the connection line part connects the first and second pad parts to each other.
摘要翻译： 显示基板包括设置在显示区域中的像素电极，设置在与显示区域相邻设置的周边区域的第一区域中的第一焊盘部分，其中第一焊盘部分电连接到驱动器电路，第二焊盘部分 衬垫部分设置在面向第一焊盘部分的周边区域的第二区域中，其中第二焊盘部分电连接到将传输信号传递到驱动器电路的柔性电路膜，以及布置在第二焊盘部分之间的区域中的连接线部分 所述第一和第二焊盘部分为垂直线型，其中连接线部分将第一和第二焊盘部分彼此连接。
-
-
-
-
搜索结果
5 条记录 (耗时 0.018 秒)
