Abstract:
A display device that may be driven at both frequencies of 120 Hz and 240 Hz, includes a plurality of pixels arranged in a column direction and a row direction, a plurality of data lines connected with one of the pixels of a j-th row (‘j’ is a natural number) and one of the pixels of a (j+1)-th row in k-th column (‘k’ is a natural number), and connected with one of the pixels of a (j+2)-th row and one of the pixels of a (j+3)-th row in (k−1)-th column, a first gate circuit part configured to apply a gate signal to a (4m−3)-th gate line row (‘m’ is a natural number), a second gate circuit part configured to apply a gate signal to a (4m−2)-th gate line row, a third gate circuit part configured to apply a gate signal to a (4m−1)-th gate line row and a fourth gate circuit part configured to apply a gate signal to a 4m-th gate line row.
Abstract:
A display substrate includes a base substrate including a display area and a peripheral area surrounding the display area, a switching element in the display area, a main-test-line in the peripheral area, extending in the second direction and electrically connected with a data line, a sub-test-line in the peripheral area, and a test pad in the peripheral area and electrically connected with the main-test-line and the sub-test-line. The switching element is electrically connected with a gate line extending in a first direction and the data line extending in a second direction crossing the first direction. The sub-test-line is electrically connected with the data line. The sub-test-line is in a different layer from the main-test-line.
Abstract:
A display device that may be driven at both frequencies of 120 Hz and 240 Hz, includes a plurality of pixels arranged in a column direction and a row direction, a plurality of data lines connected with one of the pixels of a j-th row (‘j’ is a natural number) and one of the pixels of a (j+1)-th row in k-th column (‘k’ is a natural number), and connected with one of the pixels of a (j+2)-th row and one of the pixels of a (j+3)-th row in (k−1)-th column, a first gate circuit part configured to apply a gate signal to a (4m−3)-th gate line row (‘m’ is a natural number), a second gate circuit part configured to apply a gate signal to a (4m−2)-th gate line row, a third gate circuit part configured to apply a gate signal to a (4m−1)-th gate line row and a fourth gate circuit part configured to apply a gate signal to a 4m-th gate line row.
Abstract:
A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.
Abstract:
A display apparatus includes a display panel comprising a plurality of gate lines connected to a plurality of pixel rows, a plurality of data lines connected to a plurality of a pixel columns, at least one dummy pixel row disposed in a peripheral area surrounding a display area in which the plurality of pixel rows and the plurality of a pixel columns are disposed, and at least one dummy gate line connected to the dummy pixel row and a data driver circuit configured to provide the dummy pixel row with a dummy data signal, the dummy data signal having a level that differs from a data signal of a pixel column adjacent to the dummy pixel row.
Abstract:
A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.