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公开(公告)号：US09397120B2
公开(公告)日：2016-07-19
申请号：US14224779
申请日：2014-03-25
发明人： Min-Ha Hwang , Woong-Kwon Kim , In-Woo Kim , Seong-Young Lee , Kweon-Sam Hong , Dong-Hyun Yoo , Beom-Hee Han
IPC分类号： H01L21/00 , H01L21/84 , G02F1/1345 , H04N5/66 , H01L27/12 , H01L29/417
CPC分类号： H01L27/124 , H01L29/41733
摘要： An array substrate includes a substrate, a plurality of gate lines extending in a first direction on the substrate, a plurality of data lines including first and second data line pairs separated by cutting portions and a plurality of active patterns electrically connected to the first and second data line pairs. The data lines extend in a second direction crossing the first direction. The active patterns overlap the cutting portion and overlap a first gate line.
摘要翻译： 阵列基板包括基板，在基板上沿第一方向延伸的多条栅极线，多条数据线，包括由切割部分分开的第一和第二数据线对以及电连接到第一和第二 数据线对。 数据线沿与第一方向交叉的第二方向延伸。 活动图案与切割部分重叠并且与第一栅极线重叠。
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公开(公告)号：US20140204006A1
公开(公告)日：2014-07-24
申请号：US14223883
申请日：2014-03-24
发明人： Nam-Soo Kang , Seong-Young Lee , Sung-Man Kim , Seung-Hwan Moon
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G02F1/136286 , G09G3/36 , G09G3/3611 , G09G3/3648 , G09G3/3655 , G09G2300/0413 , G09G2300/0426 , G09G2300/0452 , G09G2310/08 , G09G2320/0209 , G09G2320/0247
摘要： A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.
摘要翻译： 显示装置包括具有像素行和像素列的像素矩阵，并且包括具有切换元件的像素，交替元件交替地位于每个像素列的上侧和下侧附近的角落处，并且交替地位于靠近上侧和下侧的拐角处， 交替地在每个像素列的左侧和右侧的角落处; 多对栅极线传输栅极导通电压; 和多条数据线传输数据电压，其中每对栅极线设置在每个像素行的上侧和下侧，每行中的像素连接到最靠近各个开关元件的栅极线，并且每条数据线被布置 在相邻的像素列对之间并连接到成对的像素对，其中该对的一个像素具有位于最靠近相应数据线的开关元件。
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公开(公告)号：US10217434B2
公开(公告)日：2019-02-26
申请号：US15868879
申请日：2018-01-11
发明人： Dong-Gyu Kim , Seong-Young Lee , Sahng-Ik Jun , Sung-Jae Moon
IPC分类号： G09G3/36 , G02F1/133 , G02F1/1362 , G02F1/1343 , G02F1/1368 , G02F1/1333
摘要： A display device and a driving method therefor includes a plurality of unit pixels arranged in a matrix form, a plurality of gate lines extending in a row direction and connected to the unit pixels, respectively, pluralities of first and second data lines extending in a column direction and connected to the unit pixels, respectively, a plurality of charge control lines extending in the row direction and connected to the unit pixels, respectively, a plurality of gate connection lines connected to at least two adjacent gate lines, respectively, and a plurality of charge connection lines connected to at least two adjacent charge control lines, respectively.
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公开(公告)号：US10026371B2
公开(公告)日：2018-07-17
申请号：US15707223
申请日：2017-09-18
发明人： Nam-Soo Kang , Seong-Young Lee , Sung-Man Kim , Seung-Hwan Moon
IPC分类号： G09G3/36 , G02F1/1362
摘要： A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.
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公开(公告)号：US09767746B2
公开(公告)日：2017-09-19
申请号：US15332827
申请日：2016-10-24
发明人： Nam-Soo Kang , Seong-Young Lee , Sung-Man Kim , Seung-Hwan Moon
IPC分类号： G09G3/36 , G02F1/1362
CPC分类号： G09G3/3614 , G02F1/136286 , G09G3/36 , G09G3/3611 , G09G3/3648 , G09G3/3655 , G09G2300/0413 , G09G2300/0426 , G09G2300/0452 , G09G2310/08 , G09G2320/0209 , G09G2320/0247
摘要： A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.
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公开(公告)号：US09588388B2
公开(公告)日：2017-03-07
申请号：US14149013
申请日：2014-01-07
发明人： Soon-Il Ahn , Seung-Soo Baek , Seong-Young Lee , Kee-Bum Park
IPC分类号： G02F1/1343 , G02F1/1362 , G02F1/1345 , G02F1/1335 , G09G3/20
CPC分类号： G09G3/3225 , G02F1/133512 , G02F1/133514 , G02F1/1345 , G02F1/13454 , G02F1/136209 , G02F1/136213 , G02F1/136286 , G02F1/1368 , G02F2201/123 , G09G3/20 , G09G3/3648 , G09G2300/04 , G09G2300/0426 , G09G2300/0439 , G09G2300/0842 , G09G2310/08 , G09G2320/0223 , Y10T29/49155
摘要： An apparatus and method of preventing signal delay in a display device according to the present invention includes a first substrate, a driving portion formed on the first substrate, a plurality of signal lines formed on the first substrate to transmit signals to the driving portion, a second substrate facing the first substrate, and a conductive member formed on the second substrate, wherein the driving portion overlaps with the conductive member, and the signal lines and the conductive member do not overlap. Accordingly, the capacitances between the signal lines may be substantially the same.
摘要翻译： 根据本发明的防止信号延迟的装置和方法包括第一基板，形成在第一基板上的驱动部分，形成在第一基板上以将信号传输到驱动部分的多条信号线， 面对第一基板的第二基板和形成在第二基板上的导电部件，其中驱动部分与导电部件重叠，并且信号线和导电部件不重叠。 因此，信号线之间的电容可以是基本上相同的。
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公开(公告)号：US20150129963A1
公开(公告)日：2015-05-14
申请号：US14224779
申请日：2014-03-25
发明人： Min-Ha Hwang , Woong-Kwon Kim , In-Woo Kim , Seong-Young Lee , Kweon-Sam Hong , Dong-Hyun Yoo , Beom-Hee Han
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L29/41733
摘要： An array substrate includes a substrate, a plurality of gate lines extending in a first direction on the substrate, a plurality of data lines including first and second data line pairs separated by cutting portions and a plurality of active patterns electrically connected to the first and second data line pairs. The data lines extend in a second direction crossing the first direction. The active patterns overlap the cutting portion and overlap a first gate line.
摘要翻译： 阵列基板包括基板，在基板上沿第一方向延伸的多条栅极线，多条数据线，包括由切割部分分开的第一和第二数据线对以及电连接到第一和第二 数据线对。 数据线沿与第一方向交叉的第二方向延伸。 活动图案与切割部分重叠并且与第一栅极线重叠。
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公开(公告)号：US09711098B2
公开(公告)日：2017-07-18
申请号：US14719483
申请日：2015-05-22
发明人： Hyung-Jun Park , Dong-Hyun Yoo , Seong-Young Lee , Byoung-Sun Na
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3648 , G09G2300/0413 , G09G2310/0205 , G09G2310/0283 , G09G2320/0209 , G09G2320/0233
摘要： A display apparatus includes a display panel comprising a plurality of gate lines connected to a plurality of pixel rows, a plurality of data lines connected to a plurality of a pixel columns, at least one dummy pixel row disposed in a peripheral area surrounding a display area in which the plurality of pixel rows and the plurality of a pixel columns are disposed, and at least one dummy gate line connected to the dummy pixel row and a data driver circuit configured to provide the dummy pixel row with a dummy data signal, the dummy data signal having a level that differs from a data signal of a pixel column adjacent to the dummy pixel row.
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公开(公告)号：US10074334B2
公开(公告)日：2018-09-11
申请号：US15601026
申请日：2017-05-22
发明人： Haeng-Won Park , Seung-Hwan Moon , Nam-Soo Kang , Sung-Jae Moon , Sung-Man Kim , Seong-Young Lee , Yong-Soon Lee
CPC分类号： G09G3/3677 , G09G2300/0426 , G11C19/184
摘要： A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.
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公开(公告)号：US09734777B2
公开(公告)日：2017-08-15
申请号：US14587788
申请日：2014-12-31
发明人： Hyung-Jun Park , Byoung-Sun Na , Seong-Young Lee , Dong-Hyun Yoo
CPC分类号： G09G3/3614 , G09G3/003 , G09G2300/0413 , G09G2330/06 , G09G2340/0435
摘要： A display device that may be driven at both frequencies of 120 Hz and 240 Hz, includes a plurality of pixels arranged in a column direction and a row direction, a plurality of data lines connected with one of the pixels of a j-th row (‘j’ is a natural number) and one of the pixels of a (j+1)-th row in k-th column (‘k’ is a natural number), and connected with one of the pixels of a (j+2)-th row and one of the pixels of a (j+3)-th row in (k−1)-th column, a first gate circuit part configured to apply a gate signal to a (4m−3)-th gate line row (‘m’ is a natural number), a second gate circuit part configured to apply a gate signal to a (4m−2)-th gate line row, a third gate circuit part configured to apply a gate signal to a (4m−1)-th gate line row and a fourth gate circuit part configured to apply a gate signal to a 4m-th gate line row.
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