Abstract:
A thin film transistor (“TFT”) array panel is provided. The TFT array panel includes an insulation substrate, a gate line formed on the insulation substrate and including a gate electrode, a data line insulated from and intersecting the gate line, and including a source electrode, a drain electrode opposite to the source electrode on the gate line, and a semiconductor formed in a layer between the data line and the gate line, and having a protruding portion extending below the drain electrode, wherein a portion of the semiconductor extending towards the drain electrode, from an area occupied by the data line, is positioned within an occupying area of the gate line including the gate electrode.
Abstract:
A display apparatus includes a display substrate and a counter substrate. The display substrate includes a first substrate and a plurality of pixel electrodes formed on the first substrate. The counter substrate includes a second substrate facing the first substrate, a common electrode formed on the second substrate, a first spacer formed on the common electrode and making contact with the display substrate, a second spacer having a first gap with the display substrate, a third spacer having a second gap larger than the first gap with the display substrate, and a fourth spacer having a third gap larger than the second gap with the display substrate.
Abstract:
A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.
Abstract:
A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.
Abstract:
An array substrate includes a base substrate, a plurality of storage voltage lines, a plurality of connecting lines, and a common voltage applying section. Pixels are formed in regions defined by a plurality of gate lines extending along a first direction and data lines extending along a second direction. The connecting lines are connected to the storage voltage lines that are formed on adjacent pixels of pixels arranged in the second direction. The common voltage applying section applies a common voltage to the storage voltage lines that are formed in a portion of the pixels arranged in the first direction. Thus, a substantially uniform current may be applied to the display area to decrease the distortion of the common voltage, thereby increasing a liquid crystal display device's display quality.