公开(公告)号：US20220108667A1

公开(公告)日：2022-04-07

申请号：US17493097

申请日：2021-10-04

Applicant: Samsung Display Co., Ltd.

Inventor： JONG-WOONG PARK ,  SUK HOON KU ,  Seok Jeong SONG

IPC: G09G5/10 ,  G09G3/3275

Abstract: A data compensation circuit includes a reference frame memory device which stores reference frame data, an accumulated stress memory device which stores cumulative stress data for each of pixels, a stress data generating block which compares output image data with the reference frame data to generate stress data for each of the pixels, a memory control block which adds the stress data to the cumulative stress data to update the cumulative stress data and a compensating block which generates the output image data by generating afterimage compensation data for each of the pixels based on the cumulative stress data and compensating input image data based on the afterimage compensation data.

公开(公告)号：US20170194401A1

公开(公告)日：2017-07-06

申请号：US15209152

申请日：2016-07-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SEONG MIN CHO ,  SUK HOON KU

IPC: H01L27/32 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L27/3248 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/3262 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/7869

Abstract: The described technology relates generally to a thin film transistor for a display device and an organic light emitting diode display device including the same. An exemplary embodiment provides a thin film transistor for a display device, including: a substrate; a semiconductor that is disposed on the substrate and includes a channel, and a source region and a drain region disposed at opposite sides of the channel; a gate insulating layer that includes a first gate insulating layer disposed on the substrate and the semiconductor, and a second gate insulating layer disposed on the first gate insulating layer and overlapping the channel; a gate electrode disposed on the second gate insulating layer; an interlayer insulating layer disposed directly on the first gate insulating layer and the gate electrode; and a source electrode and a drain electrode that are disposed on the interlayer insulating layer and are connected to the semiconductor, wherein a thickness of a portion of the gate insulating layer overlapped with the gate electrode may be larger than that of a portion of the gate insulating layer overlapped with the source region and that of a portion of the gate insulating layer overlapped with the drain region.