公开(公告)号：US08854292B2

公开(公告)日：2014-10-07

申请号：US14054199

申请日：2013-10-15

Applicant: Samsung Display Co., Ltd.

Inventor： Jong-Heon Han ,  Seob Shin ,  Jae-Kyoung Kim

IPC: G09G3/36 ,  G11C27/04 ,  G11C19/18 ,  H03K17/16 ,  G11C19/28

CPC classification number: G11C27/04 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/18 ,  G11C19/28 ,  H03K17/162

Abstract: A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section.

公开(公告)号：US20140043222A1

公开(公告)日：2014-02-13

申请号：US14054199

申请日：2013-10-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jong-Heon Han ,  Seob Shin ,  Jae-Kyoung Kim

IPC: G11C27/04 ,  G09G3/36 ,  H03K17/16

CPC classification number: G11C27/04 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/18 ,  G11C19/28 ,  H03K17/162

Abstract: A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section.

Abstract translation: 栅极驱动电路包括彼此相继连接的多个级。 每个级包括充电部分，驱动部分，放电部分，保持部分和保持控制部分。 驱动部分提取高电平的第一时钟信号以输出门信号。 放电部将第一节点的电压电位放电至第一截止电压。 保持部将第一节点的电位电压保持为第一截止电压。 保持控制部分接收第一时钟信号和第二时钟信号。 保持控制部根据第二时钟信号，通过第二节点将保持部的电压电位保持为第二截止电压，以防止保持部的浮动。

公开(公告)号：US08717344B2

公开(公告)日：2014-05-06

申请号：US13931630

申请日：2013-06-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jong-Heon Han ,  Seob Shin ,  Sung-Il Lee

IPC: G02F1/13

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0465 ,  G09G2310/0297

Abstract: A display device, includes: a plurality of thin film transistors which comprise a gate electrode, a source electrode and a drain electrode; a plurality of pixel electrodes which are respectively connected to the drain electrode of the thin film transistors; a plurality of gate lines which are respectively disposed to the opposite edge parts of the pixel electrodes in a lengthwise direction of the pixel electrodes, and connected to the gate electrode of the thin film transistors; and a plurality of data lines which are respectively disposed to a single edge part of the pixel electrodes in a widthwise direction of the pixel electrodes, and connected to the source electrode of the thin film transistors, a pair of pixel electrodes adjoining each other to interpose the single data line therebetween, and a pair of thin film transistors which are respectively connected to the pair of pixel electrodes being connected with the same single data line.

Abstract translation: 一种显示装置，包括：多个薄膜晶体管，其包括栅电极，源电极和漏电极; 分别连接到薄膜晶体管的漏电极的多个像素电极; 多个栅极线，其分别设置在像素电极的长度方向上的相对边缘部分，并连接到薄膜晶体管的栅电极; 以及多个数据线，其分别设置在像素电极的宽度方向上的像素电极的单个边缘部分上并连接到薄膜晶体管的源电极，一对彼此相邻以插入的像素电极 其间的单个数据线以及分别连接到该对像素电极的一对薄膜晶体管与相同的单个数据线连接。