公开(公告)号：US12027535B2

公开(公告)日：2024-07-02

申请号：US16830675

申请日：2020-03-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  H01L29/786 ,  G06F3/041 ,  G09G3/20 ,  G11C19/28 ,  G11C27/04 ,  H01L21/8226 ,  H01L27/02

CPC classification number: H01L27/1255 ,  H01L27/124 ,  H01L29/7869 ,  G06F3/041 ,  G09G3/2092 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  G11C27/04 ,  H01L21/8226 ,  H01L27/0207 ,  H01L27/1225

Abstract: The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

公开(公告)号：US11955167B2

公开(公告)日：2024-04-09

申请号：US17574363

申请日：2022-01-12

Applicant: Northwestern University

Inventor： Jie Gu ,  Zhengyu Chen

IPC: G11C16/34 ,  G06F7/544 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C27/04 ,  H03M1/00 ,  H03M1/46

CPC classification number: G11C11/4096 ,  G06F7/5443 ,  G11C11/4085 ,  G11C11/4094 ,  G11C27/04 ,  H03M1/001 ,  H03M1/462

Abstract: Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a read bitline; a switch transistor M2 in electrical communication with the read-access transistor M1; a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.

公开(公告)号：US20150016584A1

公开(公告)日：2015-01-15

申请号：US14226760

申请日：2014-03-26

Applicant: Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC Optoelectronics Co., Ltd.

Inventor： Dongliang DUN ,  Zhiqiang XIA

IPC: G11C27/04

CPC classification number: G11C27/04 ,  G09G3/3266 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register unit, a display panel including the shift register unit and a display device including the display panel are provided. The shift register unit includes a driving module, an output module, a first transistor, and a second transistor. By connecting a second electrode of the first transistor in the shift register unit with an output terminal of the shift register unit, even if a channel width of the second transistor is considerably smaller than a theoretical design value, abnormal output of the shift register unit can be avoided.

Abstract translation: 提供了移位寄存器单元，包括移位寄存器单元的显示面板和包括显示面板的显示设备。 移位寄存器单元包括驱动模块，输出模块，第一晶体管和第二晶体管。 通过将移位寄存器单元中的第一晶体管的第二电极与移位寄存器单元的输出端子连接，即使第二晶体管的沟道宽度明显小于理论设计值，移位寄存器单元的异常输出也可以 避免。

公开(公告)号：US20130201745A1

公开(公告)日：2013-08-08

申请号：US13761048

申请日：2013-02-06

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C17/08 ,  G11C19/28 ,  G11C17/16

CPC classification number: G11C17/08 ,  G11C8/18 ,  G11C11/1659 ,  G11C11/1675 ,  G11C17/12 ,  G11C17/16 ,  G11C17/18 ,  G11C19/28 ,  G11C27/04 ,  H03K3/00 ,  H03K3/35606

Abstract: A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2n−1 address spaces from an n-bit address. The registers used in the address generator can have two latches. Each latch has two cross-coupled inverters with two outputs coupled to the drains of two MOS input devices, respectively. The inputs of the latch are coupled to the gates of the MOS input devices, respectively. The sources of the MOS input devices are coupled to the drains of at least one MOS device(s), whose gate(s) are coupled to a clock signal and whose source(s) are coupled to a supply voltage. The two latches can be constructed in serial with the outputs of the first latch coupled to the inputs of the second latch.

Abstract translation: 公开了低密度一次可编程（OTP）存储器，以实现外围电路中的低门数和低开销以节省成本。 最大长度线性反馈移位寄存器（LFSR）可用于从n位地址生成2n-1个地址空间。 在地址发生器中使用的寄存器可以有两个锁存器。 每个锁存器具有两个交叉耦合的反相器，其两个输出分别耦合到两个MOS输入装置的漏极。 锁存器的输入分别耦合到MOS输入装置的栅极。 MOS输入设备的源极耦合到至少一个MOS器件的漏极，其栅极被耦合到时钟信号并且其源极耦合到电源电压。 两个锁存器可以与耦合到第二锁存器的输入的第一锁存器的输出串联构造。

公开(公告)号：US20100171728A1

公开(公告)日：2010-07-08

申请号：US12533771

申请日：2009-07-31

Applicant: Jong-Heon Han ,  Seob Shin ,  Jae-Kyoung Kim

Inventor： Jong-Heon Han ,  Seob Shin ,  Jae-Kyoung Kim

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G11C27/04 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/18 ,  G11C19/28 ,  H03K17/162

Abstract: A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section.

Abstract translation: 栅极驱动电路包括彼此相继连接的多个级。 每个级包括充电部分，驱动部分，放电部分，保持部分和保持控制部分。 驱动部分提取高电平的第一时钟信号以输出门信号。 放电部将第一节点的电压电位放电至第一截止电压。 保持部将第一节点的电位电压保持为第一截止电压。 保持控制部分接收第一时钟信号和第二时钟信号。 保持控制部根据第二时钟信号，通过第二节点将保持部的电压电位保持为第二截止电压，以防止保持部的浮动。

公开(公告)号：US20060090028A1

公开(公告)日：2006-04-27

申请号：US10952454

申请日：2004-09-27

Applicant: Michael Anthony ,  Edward Kohler ,  Daniel Santiago

Inventor： Michael Anthony ,  Edward Kohler ,  Daniel Santiago

IPC: G06F12/14

CPC classification number: G11C27/04

Abstract: A sample-and-hold device provides output charge pairs which represent samples of a continuous-time differential input voltage. The device uses charge-coupled device elements in a symmetrical structure for splitting a constant input charge into a signal-dependent output charge pair. It is capable of operation at higher speed and with higher dynamic range than similar prior-art devices.

Abstract translation: 采样保持器件提供表示连续时间差分输入电压的样本的输出电荷对。 该器件使用对称结构的电荷耦合器件元件，用于将恒定的输入电荷分解成与信号相关的输出电荷对。 它能够以比现有技术的装置更高的速度和更高的动态范围进行操作。

公开(公告)号：US06787749B1

公开(公告)日：2004-09-07

申请号：US09512145

申请日：2000-02-23

Applicant: Zhimin Zhou ,  Eric R. Fossum ,  Bedabrata Pain

Inventor： Zhimin Zhou ,  Eric R. Fossum ,  Bedabrata Pain

IPC: H01L2700

CPC classification number: G11C27/04 ,  H04N5/347 ,  H04N5/3658

Abstract: An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Abstract translation: 一种图像传感器，其可操作以根据接收的光电平改变输出空间分辨率，同时保持期望的信噪比。 添加具有可调整尺寸的像素补丁中的相邻像素的信号以增加图像亮度和信噪比。 一个实施例包括用于接收输入信号的传感器阵列，用于临时存储全帧的帧存储器阵列，以及用于统一的列并行信号求和的自校准列积分器的阵列。 列积分器能够基本上消除固定模式噪声。

公开(公告)号：US4739396C1

公开(公告)日：2002-07-09

申请号：US42513682

申请日：1982-09-27

Applicant: HYATT GILBERT P

Inventor： HYATT GILBERT P

IPC: B60R16/02 ,  B60R16/037 ,  F21V23/00 ,  G01S7/52 ,  G01S15/89 ,  G02F1/133 ,  G03F9/00 ,  G04G99/00 ,  G05B19/35 ,  G05B19/408 ,  G05B19/409 ,  G05B19/4093 ,  G05B19/414 ,  G06F13/16 ,  G06J1/00 ,  G07G1/12 ,  G10L19/00 ,  G11C11/56 ,  G11C19/28 ,  G11C19/36 ,  G11C27/00 ,  G11C27/02 ,  G11C27/04 ,  H03H17/02 ,  H04N5/74 ,  H04N9/31

CPC classification number: B60R16/0373 ,  F21V23/00 ,  G01S7/52026 ,  G01S15/897 ,  G01S15/8977 ,  G02F1/13318 ,  G03F9/7049 ,  G03F9/7088 ,  G04G99/006 ,  G05B19/351 ,  G05B19/408 ,  G05B19/4083 ,  G05B19/4086 ,  G05B19/409 ,  G05B19/4093 ,  G05B19/414 ,  G05B19/4142 ,  G05B2219/23094 ,  G05B2219/33182 ,  G05B2219/34023 ,  G05B2219/34098 ,  G05B2219/34471 ,  G05B2219/34472 ,  G05B2219/35262 ,  G05B2219/35263 ,  G05B2219/35373 ,  G05B2219/35381 ,  G05B2219/35431 ,  G05B2219/35436 ,  G05B2219/35453 ,  G05B2219/35472 ,  G05B2219/35554 ,  G05B2219/35588 ,  G05B2219/36152 ,  G05B2219/36227 ,  G05B2219/36333 ,  G05B2219/36366 ,  G05B2219/36379 ,  G05B2219/36395 ,  G05B2219/36502 ,  G05B2219/36503 ,  G05B2219/36506 ,  G05B2219/36546 ,  G05B2219/41021 ,  G05B2219/42237 ,  G05B2219/45214 ,  G05B2219/45215 ,  G05B2219/49221 ,  G05B2219/50047 ,  G05B2219/50048 ,  G05B2219/50083 ,  G05B2219/50151 ,  G06F13/16 ,  G06J1/00 ,  G07G1/12 ,  G10L19/00 ,  G11C7/1042 ,  G11C7/16 ,  G11C11/565 ,  G11C13/0033 ,  G11C13/04 ,  G11C16/3418 ,  G11C16/3431 ,  G11C19/287 ,  G11C19/36 ,  G11C27/00 ,  G11C27/024 ,  G11C27/04 ,  H03H17/0291

公开(公告)号：US5999462A

公开(公告)日：1999-12-07

申请号：US205200

申请日：1998-12-04

Applicant: Masayuki Katakura ,  Masashi Takeda

Inventor： Masayuki Katakura ,  Masashi Takeda

IPC: G11C7/22 ,  G11C27/04 ,  G11C7/00

CPC classification number: G11C7/222 ,  G11C27/04 ,  G11C7/22

Abstract: An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

Abstract translation: 一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 将X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数设置为除了1以外没有公共除数。因此，当要选择性地扫描存储器单元时， 可以在不依赖于存储单元的位置的情况下向所有存储单元提供相同的选择条件，并且减少连接到信号写/读终端的寄生电容。

公开(公告)号：US5909026A

公开(公告)日：1999-06-01

申请号：US867835

申请日：1997-06-03

Applicant: Zhimin Zhou ,  Eric R. Fossum ,  Bedabrata Pain

Inventor： Zhimin Zhou ,  Eric R. Fossum ,  Bedabrata Pain

IPC: G11C27/04 ,  H04N5/347 ,  H04N5/365 ,  H04N5/369 ,  H04N5/374 ,  H01J40/14

CPC classification number: H04N5/347 ,  G11C27/04 ,  H04N5/3743

Abstract: An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Abstract translation: 一种图像传感器，其可操作以根据接收的光电平改变输出空间分辨率，同时保持期望的信噪比。 添加具有可调整尺寸的像素补丁中的相邻像素的信号以增加图像亮度和信噪比。 一个实施例包括用于接收输入信号的传感器阵列，用于临时存储全帧的帧存储器阵列，以及用于统一的列并行信号求和的自校准列积分器的阵列。 列积分器能够基本上消除固定模式噪声。