公开(公告)号：US20150311234A1

公开(公告)日：2015-10-29

申请号：US14795431

申请日：2015-07-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Woo PARK ,  Do-Hyun KIM ,  Young Joo CHOI ,  Dong Hoon LEE ,  Sung Haeng CHO

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，设置在基板上并且包括栅电极，包括设置在基板上的氧化物半导体的半导体层以及设置在基板上的数据线层，并且包括与栅极交叉的数据线 线，连接到数据线的源电极和面对源电极的漏电极。 此外，数据线层的数据线，源电极或漏电极中的至少一个包括阻挡层和设置在阻挡层上的主配线层。 主配线层包括铜或铜合金。 此外，阻挡层包括金属氧化物，并且金属氧化物包括锌。

公开(公告)号：US20170154897A1

公开(公告)日：2017-06-01

申请号：US15427696

申请日：2017-02-08

Applicant: Samsung Display Co., Ltd.

Inventor： Do-Hyun KIM ,  Yoon Ho KHANG ,  Dong-Hoon LEE ,  Sang Ho PARK ,  Se Hwan YU ,  Cheol Kyu KIM ,  Yong-Su LEE ,  Sung Haeng CHO ,  Chong Sup CHANG ,  Dong Jo KIM ,  Jung Kyu LEE

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

公开(公告)号：US20160148958A1

公开(公告)日：2016-05-26

申请号：US15010497

申请日：2016-01-29

Applicant: Samsung Display Co., Ltd.

Inventor： Do-Hyun KIM ,  Yoon Ho KHANG ,  Dong-Hoon LEE ,  Sang Ho PARK ,  Se Hwan YU ,  Cheol Kyu KIM ,  Yong-Su LEE ,  Sung Haeng CHO ,  Chong Sup CHANG ,  Dong Jo KIM ,  Jung Kyu LEE

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract translation: 薄膜晶体管阵列面板包括：设置在基板上的栅极布线层; 设置在所述栅极布线层上的氧化物半导体层; 以及数据布线层，其设置在所述氧化物半导体层上，所述数据布线层包括包含铜的主布线层和设置在所述主布线层上并包括铜合金的覆盖层。