公开(公告)号：US20160300950A1

公开(公告)日：2016-10-13

申请号：US14887483

申请日：2015-10-20

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun LEE ,  Ki Won Kim ,  Yoo Ho Kim ,  Joon Geol Kim ,  Doo Hyoung Lee

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L21/4763 ,  H01L29/22 ,  H01L29/66 ,  H01L21/44 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/44 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1259 ,  H01L29/22 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78618

Abstract: A thin film transistor array panel includes a gate line disposed on a substrate, the gate line including a gate electrode, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the substrate, the semiconductor layer including an oxide semiconductor, a data line disposed on the substrate and crossing the gate line, a data line layer including a source electrode connected to the data line and a drain electrode facing the source electrode, and a passivation layer covering the source electrode and the drain electrode. The data line layer includes copper or a copper alloy, and the semiconductor layer includes a copper doped oxide semiconductor. A content of copper doped on the oxide semiconductor is 0.2% to 0.82%.

Abstract translation: 薄膜晶体管阵列面板包括设置在基板上的栅极线，栅极线包括栅极电极，设置在栅电极上的栅极绝缘层，设置在基板上的半导体层，包括氧化物半导体的半导体层， 数据线，设置在基板上并与栅极线交叉;数据线层，包括连接到数据线的源电极和面对源电极的漏极，以及覆盖源电极和漏电极的钝化层。 数据线层包括铜或铜合金，并且半导体层包括掺铜氧化物半导体。 氧化物半导体上掺杂的铜的含量为0.2〜0.82％。