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1.发明授权公开(公告)号：US11906585B2
公开(公告)日：2024-02-20
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
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2.发明公开公开(公告)号：US20230194608A1
公开(公告)日：2023-06-22
申请号：US17657659
申请日：2022-04-01
发明人： A Santosh Kumar Reddy , Gunjan Mandal , Parin Rajnikant Bhuta , Raghavendra Molthati , Saikat Hazra , Sanjeeb Kumar Ghosh , Sunil Rajan , Krupal Jitendra Mehta , Praveen S. Bharadwaj
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31724
摘要： The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
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公开(公告)号：US10951441B2
公开(公告)日：2021-03-16
申请号：US16538071
申请日：2019-08-12
IPC分类号： H04L27/00 , H04L25/02 , H03K17/687 , H04L25/00 , H03F3/45
摘要： An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ‘ON’ and thereby DC-couple the input to the receiver, and cause the bypass switch to switch ‘OFF’ and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an ‘OFF’ state of the bypass switch while the input is AC-coupled.
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