公开(公告)号：US20250072098A1

公开(公告)日：2025-02-27

申请号：US18486884

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Ming He ,  Aravindh Kumar ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L21/8238 ,  H01L29/08

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

公开(公告)号：US20240347537A1

公开(公告)日：2024-10-17

申请号：US18363637

申请日：2023-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Aravindh Kumar ,  Ming He ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/823807 ,  H01L29/0865 ,  H01L29/0882

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.

公开(公告)号：US20240405128A1

公开(公告)日：2024-12-05

申请号：US18420348

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aravindh Kumar ,  Mehdi Saremi ,  Ming He ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

公开(公告)号：US20240413232A1

公开(公告)日：2024-12-12

申请号：US18356776

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Aravindh Kumar ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Ming He ,  Harsono Simka

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.