公开(公告)号：US20250072098A1

公开(公告)日：2025-02-27

申请号：US18486884

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Ming He ,  Aravindh Kumar ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L21/8238 ,  H01L29/08

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

公开(公告)号：US20240047539A1

公开(公告)日：2024-02-08

申请号：US17984025

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Mehdi Saremi ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Harsono Simka ,  Sungil Park ,  Myungil Kang ,  Kyungho Kim ,  Doyoung Choi ,  JaeHyun Park

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/41791 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/6681 ,  H01L29/8083

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.

公开(公告)号：US20240405128A1

公开(公告)日：2024-12-05

申请号：US18420348

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aravindh Kumar ,  Mehdi Saremi ,  Ming He ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

公开(公告)号：US11705363B2

公开(公告)日：2023-07-18

申请号：US17326973

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Harsono Simka ,  Rebecca Park

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76813 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20240413232A1

公开(公告)日：2024-12-12

申请号：US18356776

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Aravindh Kumar ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Ming He ,  Harsono Simka

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.

公开(公告)号：US20230178440A1

公开(公告)日：2023-06-08

申请号：US17677329

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： MING HE ,  Jaehyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L27/0922 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0665

Abstract: Integrated circuit devices and methods of forming the integrated circuit device are provided. The methods may include providing a preliminary transistor stack including an upper sacrificial layer on a substrate, an upper active region between the substrate and the upper sacrificial layer, a lower sacrificial layer between the substrate and the upper active region, and a lower active region between the substrate and the lower sacrificial layer. The methods may further include forming lower source/drain regions on respective opposing side surfaces of the lower active region, forming a preliminary capping layer on a first lower source/drain region of the lower source/drain regions, the preliminary capping layer including a semiconductor material, converting the preliminary capping layer to a capping layer that includes an insulating material, and forming upper source/drain regions on respective opposing side surfaces of the upper active region.

公开(公告)号：US20230178420A1

公开(公告)日：2023-06-08

申请号：US17679465

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  JaeHyun Park ,  Chihak Ahn ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76283 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/6653

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

公开(公告)号：US20240347537A1

公开(公告)日：2024-10-17

申请号：US18363637

申请日：2023-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Aravindh Kumar ,  Ming He ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/823807 ,  H01L29/0865 ,  H01L29/0882

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.